IDT 89HPES24N3A, User Manual

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Notes
PES24N3A User Manual vii April 10, 2008
List of Figures
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Figure 1.1 PES24N3A Architectural Block Diagram ............................................................................1-3
Figure 1.2 I/O Expansion Application ..................................................................................................1-3
Figure 1.3 PES24N3A Logic Diagram .................................................................................................1-4
Figure 2.1 Common Clock on Upstream and Downstream (option to enable or disable Spread
Spectrum Clock) ................................................................................................................2-1
Figure 2.2 Non-Common Clock on Upstream; Common Clock on Downstream (must disable
Spread Spectrum Clock) ....................................................................................................2-2
Figure 2.3 Common Clock on Upstream; Non-Common Clock on Downstream (must disable
Spread Spectrum Clock) ....................................................................................................2-2
Figure 2.4 Non-Common Clock on Upstream and Downstream (must disable Spread Spectrum
Clock) .................................................................................................................................2-3
Figure 2.5 Fundamental Reset in Transparent Mode with Serial EEPROM initialization ....................2-6
Figure 2.6 Power Enable Controlled Reset Output Mode Operation ..................................................2-8
Figure 2.7 Power Good Controlled Reset Output Mode Operation .....................................................2-9
Figure 3.1 Simplified Switch Core U-Bus and D-Bus Datapath ...........................................................3-3
Figure 3.2 U-Bus Arbitration ................................................................................................................3-7
Figure 4.1 Port Lane Reversal for Maximum Link Width of x2 (MAXLNKWDTH[5:0]=0x2) ................4-2
Figure 4.2 Port Lane Reversal for Maximum Link Width of x4 (MAXLNKWDTH[5:0]=0x4) ................4-3
Figure 4.3 Port Lane Reversal for Maximum Link Width of x8 (MAXLNKWDTH[5:0]=0x8) ................4-4
Figure 4.4 PES24N3A ASPM Link Sate Transitions ...........................................................................4-6
Figure 6.1 SMBus Interface Configuration Examples .........................................................................6-1
Figure 6.2 Single Double Word Initialization Sequence Format ..........................................................6-3
Figure 6.3 Sequential Double Word Initialization Sequence Format ...................................................6-4
Figure 6.4 Configuration Done Sequence Format ..............................................................................6-4
Figure 6.5 Slave SMBus Command Code Format ............................................................................6-12
Figure 6.6 CSR Register Read or Write CMD Field Format ..............................................................6-13
Figure 6.7 Serial EEPROM Read or Write CMD Field Format ..........................................................6-15
Figure 6.8 CSR Register Read Using SMBus Block Write/Read Transactions with PEC
Disabled ...........................................................................................................................6-16
Figure 6.9 Serial EEPROM Read Using SMBus Block Write/Read Transactions with PEC
Disabled ...........................................................................................................................6-16
Figure 6.10 CSR Register Write Using SMBus Block Write Transactions with PEC Disabled ...........6-16
Figure 6.11 Serial EEPROM Write Using SMBus Block Write Transactions with PEC Disabled ........6-17
Figure 6.12 Serial EEPROM Write Using SMBus Block Write Transactions with PEC Enabled ........6-17
Figure 6.13 CSR Register Read Using SMBus Read and Write Transactions with PEC Disabled ....6-18
Figure 7.1 PES24N3A Power Management State Transition Diagram ...............................................7-1
Figure 8.1 Hot-Plug on Switch Downstream Slots Application ............................................................8-1
Figure 8.2 Hot-Plug with Switch on Add-In Card Application ..............................................................8-2
Figure 8.3 Hot-Plug with Carrier Card Application ..............................................................................8-2
Figure 8.4 PES24N3A Hot-Plug Event Signalling ...............................................................................8-5
Figure 9.1 Port Configuration Space Organization .............................................................................9-2
Figure 10.1 Diagram of the JTAG Logic ..............................................................................................10-1
Figure 10.2 State Diagram of PES24N3A’s TAP Controller ................................................................10-2
Figure 10.3 Diagram of Observe-only Input Cell .................................................................................10-4
Figure 10.4 Diagram of Output Cell ....................................................................................................10-5
Figure 10.5 Diagram of Bidirectional Cell ............................................................................................10-5
Figure 10.6 Device ID Register Format ...............................................................................................10-7