IDT 89HPES24N3A, User Manual

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IDT Configuration Registers
PES24N3A User Manual 9 - 24 April 10, 2008
Notes
PCIELCAP - PCI Express Link Capabilities (0x04C)
5 TP RO 0x0 Transactions Pending. The bridge does not issue Non-
Posted Requests on its own behalf. Therefore, this field is
hardwired to zero.
15:6 Reserved RO 0x0 Reserved field.
Bit
Field
Field
Name
Type
Default
Value
Description
3:0 MAXLNK-
SPD
RWL 0x1 Maximum Link Speed . This field indicates the supported
link speeds of the port.
1 -(gen1) 2.5 Gbps
2 -(gen2) 5 Gbps
others-reserved
9:4 MAXLNK-
WDTH
RWL HWINIT Maximum Link Width . This field indicates the maximum
link width of the given PCI Express link. This field may be
overridden to allow the link width to be forced to a smaller
value. Setting this field to a invalid or reserved value results
in x1 being used.
The initial value of this field corresponds to the link width of
the corresponding port.
0 - reserved
1 -(x1) x1 link width
2 -(x2) x2 link width
4 -(x4) x4 link width
8 -(x8) x8 link width
12 -(x12) x12 link width
16 -(x16) x16 link width
32-(x32) x32 link width
others-reserved
11:10 ASPMS RO 0x3 Active State Power Management (ASPM) Support . This
field is hardwired to 0x3 to indicate L0s and L1 Support.
14:12 L0SEL RWL see text L0s Exit Latency . This field indicates the L0s exit latency
for the given PCI Express link. This field depends of whether
a common or separate reference clock is used
When separate clocks are used, 1 us to 2 us is reported with
a read-only value of 0x5.
When a common clock is used, 256 ns to 512 ns is reported
with a read-only value of 0x3
17:15 L1EL RWL 0x2 L1 Exit Latency . This field indicates the L1 exit latency for
the given PCI Express link. Transitioning from L1 to L0
always requires 2.3 uS. Therefore, a value 2 µs to less than
4 µs is reported with a default value of 0x2.
18 CPM RWL 0x0 Clock Power Management . This bit indicates if the compo-
nent tolerates removal of the reference clock via the
“CLKREQ#” mechanism.
The PES24N3A does not support the removal of reference
clocks.
19 SDERR RWL Upstream:
0x0
Downstream:
0x1
Surprise Down Error Reporting . The PES24N3A down-
stream ports support surprise down error reporting.
Bit
Field
Field
Name
Type
Default
Value
Description