IDT 89HPES24N3A, User Manual

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IDT JTAG Boundary Scan
PES24N3A User Manual 10 - 7 April 10, 2008
Notes
SAMPLE/PRELOAD
The sample/preload instruction has a dual use. The primary use of this instruction is for preloading the
boundary scan register prior to enabling the EXTEST instruction. Failure to preload will result in unknown
random data being driven onto the output pins when EXTEST is selected. The secondary function of
SAMPLE/PRELOAD is for sampling the system state at a particular moment. Using the SAMPLE function,
the user can halt the device at a certain state and shift out the status of all of the pins and output enables at
that time.
BYPASS
The BYPASS instruction is used to truncate the boundary scan register to a single bit in length. During
system level use of the JTAG, the boundary scan chains of all the devices on the board are connected in
series. In order to facilitate rapid testing of a given device, all other devices are put into BYPASS mode.
Therefore, instead of having to shift many times to get a value through the PES24N3A, the user only needs
to shift one time to get the value from JTAG_TDI to JTAG_TDO. When the TAP controller passes through
the CAPTURE-DR state, the value in the BYPASS register is updated to be 0.
CLAMP
This instruction, listed as optional in the IEEE 1149.1 JTAG Specifications, allows the boundary scan
chain outputs to be clamped to fixed values. When the clamp instruction is issued, the bypass register is
selected between TDI and TDO and the scan chain passes through this register to devices further down-
stream.
IDCODE
The IDCODE instruction is automatically loaded when the TAP controller state machine is reset either by
the use of the JTAG_TRST_N signal or by the application of a ‘1’ on JTAG_TMS for five or more cycles of
JTAG_TCK as per the IEEE Std. 1149.1 specification. The least significant bit of this value must always be
1. Therefore, if a device has a Device ID register, it will shift out a 1 on the first shift if it is brought directly to
the SHIFT-DR TAP controller state after the TAP controller is reset. The board- level tester can then
examine this bit and determine if the device contains a Device ID register (the first bit is a 1), or if the device
only contains a BYPASS register (the first bit is 0).
However, even if the device contains a Device ID register, it must also contain a BYPASS register. The
only difference is that the BYPASS register will not be the default register selected during the TAP controller
reset. When the IDCODE instruction is active and the TAP controller is in the Shift-DR state, the thirty-two
bit value that will be shifted out of the Device ID register is shown in Figure 10.6.
Bit(s) Mnemonic Description R/W Reset
0 Reserved Reserved R 0x1
11:1 Manuf_ID Manufacturer Identity (11 bits)
This field identifies the manufacturer as IDT.
R 0x33
27:12 Part_number Part Number (16 bits)
This field identifies the silicon as PES24N3A.
R 0x801C
31:28 Version Version (4 bits)
This field identifies the silicon revision of the PES24N3A.
R silicon-
dependent
Table 10.4 System Controller Device Identification Register
Version Part Number Mnfg. ID LSB
xxxx 1000|0000|0001|1100 0000|0011|0011 1
Figure 10.6 Device ID Register Format