IDT 89HPES24N3A, User Manual

Page: 145 / 168

IDT Configuration Registers
PES24N3A User Manual 9 - 51 April 10, 2008
Notes
SWCTL - Switch Control (0x404)
11:10 PEMODE RWL HWINIT PCI Express Base Specification Mode. This field selects
the PCIe base specification operating mode for the
PES24N3A.
0x0 - reserved
0x1 - (pebase1p1) PCIe 1.1 base specification compliant
mode.
0x2 - reserved
0x3 - reserved
19:12 Reserved RO 0x0 Reserved field.
22:20 LOCKMODE RO 0x0 Lock Mode. This field reflects the current locked status of
the switch.
0x0 - (unlocked) Upstream port is unlocked
0x1 - reserved
0x2 - (port2locked) Upstream port is locked with port 2
0x3 - reserved
0x4 - (port4locked) Upstream port is locked with port 4
0x5 through 0x7 - reserved
27:23 Reserved RO 0x0 Reserved field.
31:28 MARKER RW 0x0
Sticky
Marker. This field is preserved across a hot reset and is
available for general software use.
A hot reset does not result in modification of this field.
Bit
Field
Field
Name
Type
Default
Value
Description
0 FRST RW 0x0 Fundamental Reset. Writing a one to this bit initiates a fun-
damental reset. Writing a zero has no effect. This field
always returns a value of zero when read.
See section Fundamental Reset on page 2-4 for the behav-
ior of this bit.
1 HRST RW 0x0 Hot Reset. Writing a one to this bit initiates a hot reset. Writ-
ing a zero has no effect. This field always returns a value of
zero when read.
See section Hot Reset on page 2-6 for the behavior of this
bit.
2 RSTHALT RW HWINIT
Sticky
Reset Halt. When this bit is set, all of the switch logic except
the SMBus interface remains in a reset state. In this state,
registers in the device may be initialized by the slave SMBus
interface. When this bit is cleared, normal operation ensues.
Setting or clearing this bit has no effect following a reset
operation.
This bit will be set if during serial EEPROM initialization an
error is detected or it may be intentionally set by the user
through the EEPROM code.
3 REGUN-
LOCK
RW 0x0
Sticky
Register Unlock. When this bit is set, the contents of regis-
ters and fields of type Read and Write when Unlocked
(RWL) are modified when written to. When this bit is
cleared, all registers and fields denoted as RWL become
read-only.
While the initial value of this field is cleared, it is set during a
reset operation, thus allowing serial EEPROM initialization
to modify the contents of RWL fields.
Bit
Field
Field
Name
Type
Default
Value
Description