IDT 89HPES24N3A, User Manual

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IDT Clocking, Reset, and Initialization Clock Operation
PES24N3A User Manual 2 - 6 April 10, 2008
Notes
The PES24N3A provides a reset output signal for each downstream port implemented as a GPIO alter-
nate function. When a fundamental reset occurs, all of the GPIO pins default to GPIO inputs. Therefore, the
downstream port resets are tri-stated. A system designer should use a pull-down on these signals if they
are used as reset outputs. The operation of a fundamental reset with serial EEPROM initialization (i.e.,
SWMODE[3:0] = 0x1) is illustrated in Figure 2.5.
Figure 2.5 Fundamental Reset in Transparent Mode with Serial EEPROM initialization
Hot Reset
A hot reset may be initiated by any of the following conditions:
– Reception of TS1 ordered-sets on the upstream port indicating a hot reset.
– Data link layer of the upstream port transitions to the DL_Down state.
– Writing a one to the Hot Reset (HRST) bit in the Switch Control (SWCTL) register.
The initiation of a hot reset due to the data link layer of the upstream port transitioning to the DL_Down
state may be disabled by setting the Disable Link Down Hot Reset (DLDHRST) bit in the Switch Control
(SWCTL) register. Other hot reset conditions are unaffected by this bit.
When a hot reset occurs, the following sequence is executed.
1. Each downstream port whose link is up propagates the hot reset by transmitting TS1 ordered sets
with the hot reset bit set.
2. All of the logic associated with the PES24N3A except the PLLs, SerDes, master SMBus interface,
and slave SMBus interface is reset.
3. All registers fields in all registers, except those denoted as “sticky” or Read and Write when Unlocked
(i.e, RWL), are reset to their initial value. The value of fields denoted as “sticky” or RWL is preserved
across a hot reset.
4. Link training begins. While link training is in progress, proceed to step 5.
5. The PCI Express stacks and associated logic are held in a quasi-reset state in which the following
actions occur.
– All links enter an active link training state within 20ms of the clearing of the hot reset condition.
– Within 100ms of the clearing of the fundamental reset condition, all of the stacks are able to
process configuration transactions and respond to these transactions with a configuration request
retry status completion. All other transactions are ignored.
REFCLK*
Vdd
PERSTN
SerDes
Master SMBus
Slave SMBus
Tpvperl
PLL Reset and Lock CDR Reset & Lock Ready for Normal Operation
Ready for Normal Operation
Ready Idle Serial EEPROM Initialization
11 μ s
20ms max.
50 μ s max.
Link Training
RSTHALT bit cleared
in SWCTL
Stacks in Quasi Reset State
Notes:
1) Reference Clock (REFCLK) not shown to scale.
2) The PES24N3A requires a minimum time for Tperst-clk of 1µs. The PES24N3A requires a minimum time for Tpvperl of 1ms.
3) In a system, the values of Tpvperl and Tperst-clk depend on the mechanical form factor in which the PES24N3A is used. For example,
the PCIe Card Electromechanical Specification, Revision 2.0, specifies minimum values of Tperst-clk=100µs and Tpvperl=100ms.