IDT 89HPES24N3A, User Manual

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IDT Configuration Registers
PES24N3A User Manual 9 - 55 April 10, 2008
Notes
SMBUSCTL - SMBus Control (0x428)
24 EEPROM-
DONE
RO 0x0 Serial EEPROM Initialization Done. When the switch is
configured to operate in a mode in which serial EEPROM
initialization occurs during a fundamental reset, this bit is set
when serial EEPROM initialization completes or when an
error is detected.
25 NAERR RW1C 0x0 No Acknowledge Error. This bit is set if an unexpected
NACK is observed during a master SMBus transaction. The
setting of this bit may indicate the following: that the
addressed device does not exist on the SMBus (i.e.,
addressing error); data is unavailable or the device is busy;
an invalid command was detected by the slave; or invalid
data was detected by the slave.
26 LAERR RW1C 0x0 Lost Arbitration Error. When the master SMBus interface
loses arbitration for the SMBus, it automatically re-arbitrates
for the SMBus. If the master SMBus interface loses 16 con-
secutive arbitration attempts, then the transaction is aborted
and this bit is set.
27 OTHERERR RW1C 0x0 Other Error. This bit is set if a misplaced START or STOP
condition is detected by the master SMBus interface.
28 ICSERR RW1C 0x0 Initialization Checksum Error. This bit is set if an invalid
checksum is computed during Serial EEPROM initialization
or when a configuration done command is not found in the
serial EEPROM.
29 URIA RW1C 0x0 Unmapped Register Initialization Attempt. This bit is set if
an attempt is made to initialize via serial EEPROM a register
that is not defined in the corresponding PCI configuration
space.
31:30 Reserved RO 0x0 Reserved field.
Bit
Field
Field
Name
Type
Default
Value
Description
15:0 MSMBCP RW HWINIT
Sticky
Master SMBus Clock Prescalar. This field contains a clock
prescalar value used during master SMBus transactions.
The prescalar clock period is equal to 32 ns multiplied by the
value in this field. When the field is cleared to zero or one,
the clock is stopped.
The initial value of this field is 0x0139 when the master
SMBus is configured to operate in slow mode (i.e., 100 KHz)
in the boot configuration and to 0x0053
1
when it is config-
ured to operate in fast mode (i.e., 400 KHz).
16 MSMBIOM RW 0x0
Sticky
Master SMBus Ignore Other Masters. When this bit is set,
the master SMBus proceeds with transactions regardless of
whether it won or lost arbitration.
17 ICHECKSUM RW 0x0
Sticky
Ignore Checksum Errors. When this bit is set, serial
EEPROM initialization checksum errors are ignored (i.e., the
checksum always passes).
Bit
Field
Field
Name
Type
Default
Value
Description