IDT 89HPES24N3A, User Manual

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IDT Configuration Registers
PES24N3A User Manual 9 - 52 April 10, 2008
Notes
HPCFGCTL - Hot-Plug Configuration Control (0x408)
4 PWRBDVUL RWL 0x0
Sticky
Power Budgeting Data Value Unlock. When this bit is set,
the Power Budgeting Data Value [7:0] (PWRBDV[7:0]) reg-
isters in all ports may be read and written. When this bit is
cleared, then the PWRBDV registers in all ports are read-
only.
5 DLDHRST RW 0x0
Sticky
Disable Link Down Hot Reset. When this bit is set, hot
resets due to the data link layer of the upstream port transi-
tioning to the DL_Down state are disabled.
All other hot reset conditions are unaffected by this bit.
6 DHRSTSEI RW 0x0
Sticky
Disable Hot Reset Serial EEPROM Initialization. When
this bit is set, step 6 “serial EEPROM initialization” is
skipped in the hot reset sequence described in section Hot
Reset on page 2-6 regardless of the selected switch operat-
ing mode.
7 DRO RW 0x0
Sticky
Disable Relaxed Ordering. The switch implements relaxed
ordering for TLPs with the relaxed ordering bit set. When the
DRO bit is set, the switch strongly orders all transactions
regardless of the state of the relaxed ordering bit in TLPs.
8 DP2P RW 0x0
Sticky
Disable Peer-to-Peer Transactions. When this bit is set,
all peer-to-peer transactions are disabled. In this mode,
transactions received on a downstream port which are not
destined to the upstream port are treated as an unsupported
requests.
13:9 Reserved RO 0x0 Reserved field.
14 CTDIS RW 0x0
Sticky
Disable Cut-Through Routing. When this bit is set, cut
through routing of TLPs is disabled between all ports (i.e.,
they are routed in a stored and forwarded manner). When
this bit is cleared, TLPs are routed in a cut-through manner
when possible.
15 LOCKI-
GNORE
RW 0x0
Sticky
Ignore Locked Transactions When this bit is set, all bus
locking side-effects associated with locked transactions
(e.g., MRdLk) are ignored and the TLPs are treated by the
PES24N3A as normal TLPs (e.g., are routed normally
through the switch).
31:16 Reserved RO 0x0 Reserved field.
Bit
Field
Field
Name
Type
Default
Value
Description
0 IPXAPN RW 0x0
Sticky
Invert Polarity of PxAPN. When this bit is set, the polarity
of the PxAPN input is inverted in all ports.
1 IPXPDN RW 0x0
Sticky
Invert Polarity of PxPDN. When this bit is set, the polarity
of the PxPDN input is inverted in all ports.
2 IPXPFN RW 0x0
Sticky
Invert Polarity of PxPFN. When this bit is set, the polarity
of the PxPFN input is inverted in all ports.
3 IPXMRLN RW 0x0
Sticky
Invert Polarity of PxMRLN. When this bit is set, the polarity
of the PxMRLN input is inverted in all ports.
4 IPXAIN RW 0x0
Sticky
Invert Polarity of PxAIN. When this bit is set, the polarity of
the PxAIN output is inverted in all ports.
Bit
Field
Field
Name
Type
Default
Value
Description