IDT 89HPES24N3A, User Manual

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IDT PES24N3A Device Overview
PES24N3A User Manual 1 - 9 April 10, 2008
Notes
Pin Characteristics
Note: Some input pads of the PES24N3A do not contain internal pull-ups or pull-downs. Unused
inputs should be tied off to appropriate levels. This is especially critical for unused control signal
inputs which, if left floating, could adversely affect operation. Also, any input pin left floating can
cause a slight increase in power consumption.
V
DD
APE I PCI Express Analog Power. PCI Express analog power used by the PLL
and bias generator.
V
TT
PE I PCI Express Termination Power.
V
SS
I Ground.
Function Pin Name Type Buffer
I/O
Type
Internal
Resistor
1
Notes
PCI Express
Interface PE0RN[7:0] I CML Serial link
PE0RP[7:0] I
PE0TN[7:0] O
PE0TP[7:0] O
PE2RN[7:0] I
PE2RP[7:0] I
PE2TN[7:0] O
PE2TP[7:0] O
PE4RN[7:0] I
PE4RP[7:0] I
PE4TN[7:0] O
PE4TP[7:0] O
PEREFCLKN[2:1] I LVPECL/
CML
Diff. Clock
Input
Refer to Table 9
in the
PES24N3A Data
Sheet
PEREFCLKP[2:1] I
REFCLKM I LVTTL Input pull-down
SMBus MSMBADDR[4:1] I LVTTL Input pull-up
MSMBCLK I/O STI
2
pull-up on board
MSMBDAT I/O STI pull-up on board
SSMBADDR[5,3:1] I Input pull-up
SSMBCLK I/O STI pull-up on board
SSMBDAT I/O STI pull-up on board
General Pur-
pose I/O GPIO[7:0] I/O LVTTL High Drive pull-up
Table 1.9 Pin Characteristics (Part 1 of 2)
Signal Type Name/Description
Table 1.8 Power and Ground Pins