IDT 89HPES24N3A, User Manual

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IDT Configuration Registers
PES24N3A User Manual 9 - 28 April 10, 2008
Notes
2 MRLP RWL 0x0 MRL Sensor Present . This bit is set when an MRL Sensor
is implemented for the port.
This bit is read-only and has a value of zero when the SLOT
bit in the PCIECAP register is cleared.
3 ATTIP RWL 0x0 Attention Indicator Present . This bit is set when an Atten-
tion Indicator is implemented for the port.
This bit is read-only and has a value of zero when the SLOT
bit in the PCIECAP register is cleared.
4 PWRIP RWL 0x0 Power Indicator Present . This bit is set when an Power
Indicator is implemented for the port.
This bit is read-only and has a value of zero when the SLOT
bit in the PCIECAP register is cleared.
5 HPS RWL 0x0 Hot-Plug Surprise . When set, this bit indicates that a
device present in the slot may be removed from the system
without notice.
This bit is read-only and has a value of zero when the SLOT
bit in the PCIECAP register is cleared.
6 HPC RWL 0x0 Hot-Plug Capable . This bit is set if the slot corresponding to
the port is capable of supporting hot-plug operations.
This bit is read-only and has a value of zero when the SLOT
bit in the PCIECAP register is cleared.
14:7 SPLV RW 0x0 Slot Power Limit Value . In combination with the Slot Power
Limit Scale, this field specifies the upper limit on power sup-
plied by the slot.
A Set_Slot_Power_Limit message is generated using this
field whenever this register is written or when the link transi-
tions from a non DL_Up status to a DL_Up status.
This bit is read-only and has a value of zero when the SLOT
bit in the PCIECAP register is cleared.
16:15 SPLS RW 0x0 Slot Power Limit Scale . This field specifies the scale used
for the Slot Power Limit Value (SPLV).
0x0 -(x1) 1.0x
0x1 -(xp1) 0.1x
0x2 -(xp01) 0.01x
0x3 -(xp001) 0.001x
A Set_Slot_Power_Limit message is generated using this
field whenever this register is written or when the link transi-
tions from a non DL_Up status to a DL_Up status.
This bit is read-only and has a value of zero when the SLOT
bit in the PCIECAP register is cleared.
17 EIP RWL 0x0 Electromechanical Interlock Present . This bit is set if an
electromechanical interlock is implemented on the chassis
for this slot.
This bit is read-only and has a value of zero when the SLOT
bit in the PCIECAP register is cleared.
18 NCCS RO 0x0 No Command Completed Support . Software notification is
always generated when an issued command is completed
by the hot-plug controller. Therefore, this field is hardwired
to zero.
31:19 PSLOTNUM RWL 0x0 Physical Slot Number . This field indicates the physical slot
number attached to this port. For devices interconnected on
the system board, this field should be initialized to zero.
This bit is read-only and has a value of zero when the SLOT
bit in the PCIECAP register is cleared.
Bit
Field
Field
Name
Type
Default
Value
Description