IDT 89HPES24N3A, User Manual

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Notes
PES24N3A User Manual 6 - 1 April 10, 2008
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Chapter 6
SMBus Interfaces
Introduction
The PES24N3A contains two SMBus interfaces. The slave SMBus interface provides full access to all
software visible registers in the PES24N3A, allowing every register in the device to be read or written by an
external SMBus master. The slave SMBus may also be used to initialize the serial EEPROM used for initial-
ization. The Master SMBus interface provides connection for an optional external serial EEPROM used for
initialization and optional external I/O expanders.
Six pins make up each of the two SMBus interfaces. These pins consist of an SMBus clock pin, an
SMBus data pin, and 4 SMBus address pins. As shown in Figure 6.1, the master and slave SMBuses may
be used in a unified or split configuration.
Figure 6.1 SMBus Interface Configuration Examples
In the unified configuration, shown in Figure 6.1(a), the master and slave SMBuses are tied together and
the PES24N3A acts both as an SMBus master as well as an SMBus slave on this bus. This requires that
the external SMBus master or processor that has access to the PES24N3A registers support SMBus arbi-
tration. In some systems, this external SMBus master interface may be implemented using general purpose
I/O pins on a processor or microcontroller, and thus may not support SMBus arbitration. To support these
systems, the PES24N3A may be configured to operate in a split configuration as shown in Figure 6.1(b).
Processor
PES24N3A
SSMBCLK
SSMBDAT
MSMBCLK
MSMBDAT
SMBus
Master
Other
SMBus
Devices
Serial
EEPROM
Processor
PES24N3A
SSMBCLK
SSMBDAT
MSMBCLK
MSMBDAT
SMBus
Master
Other
SMBus
Devices
Serial
EEPROM
...
...
(a) Unified Configuration
(b) Split Configuration
Hot-Plug
I/O
Expander
Hot-Plug
I/O
Expander