IDT 89HPES24N3A, User Manual

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IDT Configuration Registers
PES24N3A User Manual 9 - 21 April 10, 2008
Notes
PCI Express Capability Structure
PCIECAP - PCI Express Capability (0x040)
PCIEDCAP - PCI Express Device Capabilities (0x044)
Bit
Field
Field
Name
Type
Default
Value
Description
7:0 CAPID RO 0x10 Capability ID . The value of 0x10 identifies this capability as
a PCI Express capability structure.
15:8 NXTPTR RWL 0xC0 Next Pointer . This field contains a pointer to the next capa-
bility structure.
19:16 VER RWL 0x1 PCI Express Capability Version. This field indicates the
PCI-SIG defined PCI Express capability structure version
number.
The default value of this field is 0x1 in PCIe 1.1 mode.
23:20 TYPE RO Upstream:
0x5
Downstream:
0x6
Port Type. This field identifies the type of switch port
(upstream or downstream).
24 SLOT RWL 0x0 Slot Implemented. This bit is set when the PCI Express link
associated with this Port is connected to a slot. This field
does not apply to an upstream port and should be set to
zero.
29:25 IMN RO 0x0 Interrupt Message Number. The function is allocated none
(upstream ports) or only one (downstream ports) MSI.
Therefore, this field is set to zero.
30 TCS RWL 0x1 TCS Routing Supported. The PES24N3A supports TCS
routing. The default value of this field is 0x0 in PCIe 1.1
mode.
31 Reserved RO 0x0 Reserved field.
Bit
Field
Field
Name
Type
Default
Value
Description
2:0 MPAYLOAD RWL 0x4 Maximum Payload Size Supported . This field indicates the
maximum payload size that the device can support for
TLPs. The default value corresponds to 2048 bytes.
4:3 PFS RO 0x0 Phantom Functions Supported . This field indicates the
support for unclaimed function number to extend the num-
ber of outstanding transactions allowed by logically combin-
ing unclaimed function numbers. The value is hardwired to
0x0 to indicate that no function number bits are used for
phantom functions.
5 ETAG RWL 0x1 Extended Tag Field Support. This field indicates the maxi-
mum supported size of the Tag field as a requester.
8:6 E0AL RO 0x0 Endpoint L0s Acceptable Latency. This field indicates the
acceptable total latency that an endpoint can withstand due
to transition from the L0s state to the L0 state. The value is
hardwired to 0x0 as this field does not apply to a switch.
11:9 E1AL RO 0x0 Endpoint L1 Acceptable Latency. This field indicates the
acceptable total latency that an endpoint can withstand due
to transition from the L1 state to the L0 state. The value is
hardwired to 0x0 as this field does not apply to a switch.