IDT 89HPES24N3A, User Manual

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IDT Configuration Registers
PES24N3A User Manual 9 - 26 April 10, 2008
Notes
PCIELSTS - PCI Express Link Status (0x052)
5 LRET RW 0x0 Link Retrain . Writing a one to this field initiates Link retrain-
ing by directing the Physical Layer LTSSM to the Recovery
state. This field always returns zero when read.
It is permitted to set this bit while simultaneously modifying
other fields in this register. When this is done, all modifica-
tions that affect link retraining are applied in the subsequent
retraining.
For compliance with the PCIe specification, this bit has no
effect on the upstream port when the REGUNLOCK bit is
cleared in the SWCTL register. In this mode the field is hard-
wired to zero. When the REGUNLOCK bit is set, writing a
one to the LRET bit initiates link retraining on the upstream
port.
6 CCLK RW 0x0 Common Clock Configuration . When set, this bit indicates
that this component and the component at the opposite end
of the link are operating with a distributed common refer-
ence clock.
7 ESYNC RW 0x0 Extended Sync . When set this bit forces transmission of
additional ordered sets when exiting the L0s state and when
in the recovery state.
8 CLKP-
WRMGT
RO 0x0 Enable Clock Power Management . The PES24N3A does
not support this feature.
9 HWAWDTH-
DIS
RW 0x0 Hardware Autonomous Width Disable . When set, this bit
disables hardware from changing the link width for reasons
other than attempting to correct for unreliable link operation
by reducing the link width.
This field is read-only zero in PCIe 1.1 mode.
10 LBWINTEN RW 0x0 Link Bandwidth Management Interrupt Enable . When
set, this bit enables the generation of an interrupt to indicate
that the LBWSTS bit has been set in the PCIELSTS register.
If the LBN field in the PCIELCAP register is cleared, this
field is hardwired to zero.
This field is read-only zero in PCIe 1.1 mode.
11 LABWINTEN RW 0x0 Link Autonomous Bandwidth Interrupt Enable . When
set, this bit enables the generation of an interrupt to indicate
that the LABWSTS bit has been set in the PCIELSTS regis-
ter.
If the LBN field in the PCIELCAP register is cleared, this
field is hardwired to zero.
This field is read-only zero in PCIe 1.1 mode.
15:12 Reserved RO 0x0 Reserved field.
Bit
Field
Field
Name
Type
Default
Value
Description
3:0 LS RO 0x1 Link Speed . This field indicates the current link speeds of
the port.
1 -(gen1) 2.5 Gbps
2 -(gen2) 5 Gbps
others-reserved
9:4 LW RO HWINIT Link Width . This field indicates the negotiated width of the
link.
Bit
Field
Field
Name
Type
Default
Value
Description