IDT 89HPES24N3A, User Manual

Page: 119 / 168

IDT Configuration Registers
PES24N3A User Manual 9 - 25 April 10, 2008
Notes
PCIELCTL - PCI Express Link Control (0x050)
20 DLLLA RWL Upstream:
0x0
Downstream:
0x1
Data Link Layer Link Active Reporting . The PES24N3A
downstream ports support the capability of reporting the
DL_Active state of the data link control and management
State machine.
This field is not applicable for the upstream port and must be
zero.
21 LBN RWL Upstream:
0x0
Downstream:
0x1
Link Bandwidth Notification Capability . When set, this bit
indicates support for the link bandwidth notification status
and interrupt mechanisms. The PES24N3A downstream
ports support the capability.
This field is not applicable for the upstream port and must be
zero.
The default value of this field for all ports is 0x0 in PCIe 1.1
mode.
23:22 Reserved RO 0x0 Reserved field.
31:24 PORTNUM RO Port 0: 0x0
Port 2: 0x2
Port 4: 0x4 Port Number . This field indicates the PCI express port num-
ber for the corresponding link.
Bit
Field
Field
Name
Type
Default
Value
Description
1:0 ASPM RW 0x0 Active State Power Management (ASPM) Control . This
field controls the level of ASPM supported by the link. The
initial value corresponds to disabled. The value contained in
Serial EEPROM may override this default value
0x0 -(disabled) disabled
0x1 -(l0s) L0s enable entry
0x2 -(l1) L1 enable entry
0x3 -(l0sl1) L0s and L1 enable entry
2 Reserved RO 0x0 Reserved field.
3 RCB RO 0x0 Read Completion Boundary . This field is not applicable
and is hardwired to zero.
4 LDIS RW 0x0 Link Disable. When set in a downstream port, this bit dis-
ables the link.
For compliance with the PCIe specification, this bit has no
effect on the upstream port when the REGUNLOCK bit is
cleared in the SWCTL register. In this mode the field is hard-
wired to zero. When the REGUNLOCK bit is set, writing a
one to the LDIS bit disables the upstream link.
Bit
Field
Field
Name
Type
Default
Value
Description