700
CKIO
A12 or A10
RD/
WR
CSn
RAS
CAS
BS
DQMxx
CKE
A25 to A16
A15 to A0
Tp
Tr
Tc1
Tc2/Td1
Tc3/Td2
Tc4/Td3
Td4
D31 to D0
t
AD
t
AD
t
CSD3
t
CSD3
t
RWD
t
RWD
t
RWD
t
RASD2
t
RASD2
t
DQMD
t
DQMD
t
DQMD
t
BSD
t
BSD
t
DAKD1
t
DAKD1
(High)
t
AD
t
AD
t
AD
t
AD
t
AD
t
AD
t
RDS2
t
RDH2
t
RDS2
t
RDH2
t
AD
Row address
Read command
Row
address
Row
address
Column address
t
CASD2
t
CASD2
DACKn
Figure 23.32 Synchronous DRAM Burst Read Bus Cycle
(RAS Down, Different Row Address, TPC = 0, RCD = 0, CAS Latency = 1)
Summary of Contents for SH7709S
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