234
Table 10.3
Physical Address Space Map
Area Connectable Memory
Physical Address
Capacity
Access Size
0
Ordinary memory
*
1
, burst ROM
H'00000000 to H'03FFFFFF
64 Mbytes 8, 16, 32
*
2
H'00 H'20000000
×
n to
H'03 H'20000000
×
n
Shadow
n: 1–6
1
Internal I/O registers
*
7
H'04000000 to H'07FFFFFF
64 Mbytes 8, 16, 32
*
3
H'04 H'20000000
×
n to
H'07 H'20000000
×
n
Shadow
n: 1–6
2
Ordinary memory
*
1
,
H'08000000 to H'0BFFFFFF
64 Mbytes 8, 16, 32
*
3,
*
4
synchronous DRAM
H'08 H'20000000
×
n to
H'0B H'20000000
×
n
Shadow
n: 1–6
3
Ordinary memory
*
1
,
H'0C000000 to H'0FFFFFFF
64 Mbytes 8, 16, 32
*
3,
*
4
synchronous DRAM
H'0C H'20000000
×
n to
H'0F H'20000000
×
n
Shadow
n: 1–6
4
Ordinary memory
*
1
H'10000000 to H'13FFFFFF
64 Mbytes 8, 16, 32
*
3
H'10 H'20000000
×
n to
H'13 H'20000000
×
n
Shadow
n: 1–6
5
Ordinary memory
*
1
, PCMCIA,
burst ROM
H'14000000 to H'15FFFFFF
32 Mbytes 8, 16, 32
*
3,
*
5
Ordinary memory, burst ROM
H'16000000 to H'17FFFFFF
32 Mbytes
H'14 H'20000000
×
n to
H'17 H'20000000
×
n
Shadow
n: 1–6
6
Ordinary memory
*
1
, PCMCIA,
H'18000000 to H'19FFFFFF
32 Mbytes 8, 16, 32
*
3,
*
5
burst ROM
H'1A000000 to H'1BFFFFFF
H'18 H'20000000
×
n to
H'1B H'20000000
×
n
Shadow
n: 1–6
7
*
6
Reserved area
H'1C H'20000000
×
n
to H'1F H'20000000
×
n
n: 0–7
Notes:
*
1 Memory with interface such as SRAM or ROM.
*
2 Use external pin to specify memory bus width.
*
3 Use register to specify memory bus width.
*
4 With synchronous DRAM interfaces, bus width must be 16 or 32 bits.
*
5 With PCMCIA interface, bus width must be 8 or 16 bits.
*
6 Do not access the reserved area. If the reserved area is accessed, correct operation
cannot be guaranteed.
*
7 When the control register in area 1 is not used for address translation by the MMU, set
the first three bits of the logical address to 101 for allocation to the P2 space.
Summary of Contents for SH7709S
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