161
7.2.5
Break Address Mask Register B (BAMRB)
BAMRB is a 32-bit read/write register. BAMRB specifies bits masked in the break address
specified by BARB. A power-on reset initializes BAMRB to H'00000000.
Bit:
31
30
29
28
27
26
25
24
BAMB31 BAMB30 BAMB29 BAMB28 BAMB27 BAMB26 BAMB25 BAMB24
Initial value:
0
0
0
0
0
0
0
0
R/W:
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Bit:
23
22
21
20
19
18
17
16
BAMB23 BAMB22 BAMB21 BAMB20 BAMB19 BAMB18 BAMB17 BAMB16
Initial value:
0
0
0
0
0
0
0
0
R/W:
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Bit:
15
14
13
12
11
10
9
8
BAMB15 BAMB14 BAMB13 BAMB12 BAMB11 BAMB10 BAMB9
BAMB8
Initial value:
0
0
0
0
0
0
0
0
R/W:
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Bit:
7
6
5
4
3
2
1
0
BAMB7
BAMB6
BAMB5
BAMB4
BAMB3
BAMB2
BAMB1
BAMB0
Initial value:
0
0
0
0
0
0
0
0
R/W:
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Bits 31 to 0—Break Address Mask Register B31 to B0 (BAMB31 to BAMB0): Specifies bits
masked in the channel B break address bits specified by BARB (BAB31—BAB0).
Bits 31 to 0:
BAMBn
Description
0
Break address BABn of channel B is included in the break condition (Initial value)
1
Break address BABn of channel B is masked and is not included in the break
condition
n = 31 to 0
Summary of Contents for SH7709S
Page 2: ...Hitachi SuperH RISC engine SH7709S Hardware Manual ADE 602 250 Rev 1 0 09 21 01 Hitachi Ltd ...
Page 75: ...56 ...
Page 107: ...88 ...
Page 125: ...106 ...
Page 139: ...120 ...
Page 203: ...184 ...
Page 245: ...226 ...
Page 411: ...392 ...
Page 609: ...590 ...
Page 635: ...616 ...
Page 663: ...644 ...
Page 679: ...660 ...