287
Transfer source address
Transfer destination address
+4
+8
+12
A25-A0
CKIO
CSn
RAS
CAS
WEn
RD/
WR
DACKn
D31-D0
Data read cycle
(1st cycle)
(2nd cycle)
Data write cycle
Note: In transfer between external memories, with DACK output in the read cycle, DACK
output timing is the same as that of
CSn
.
Figure 10.15 Example of DMA Transfer Timing in the Direct Address Mode in Dual Mode
(16-byte Transfer, Transfer Source: Synchronous DRAM, Transfer Destination: Normal
Memory)
Summary of Contents for SH7709S
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