142
6.3.6
Interrupt Request Register 0 (IRR0)
IRR0 is an 8-bit register that indicates interrupt requests from external input pins IRQ0 to IRQ5
and PINT0 to PINT15. This register is initialized to H'00 by a power-on reset or manual reset, but
is not initialized in standby mode.
Bit:
7
6
5
4
3
2
1
0
PINT0R PINT1R
IRQ5R
IRQ4R
IRQ3R
IRQ2R
IRQ1R
IRQ0R
Initial value:
0
0
0
0
0
0
0
0
R/W:
R
R
R/W
R/W
R/W
R/W
R/W
R/W
When clearing an IRQ5R–IRQ0R bit to 0, read the bit while bit set to 1, and then write 0. Only 0
can be written to bits IRQ5R–IRQ0R.
Bit 7—PINT0 to PINT7 Interrupt Request (PINT0R): Indicates whether there is interrupt
request input to pins PINT0 to PINT7.
Bit 7: PINT0R
Description
0
No interrupt request to pins PINT0 to PINT7
(Initial value)
1
Interrupt to pins PINT0 to PINT7
Bit 6—PINT8 to PINT15 Interrupt Request (PINT1R): Indicates whether there is interrupt
request input to pins PINT8 to PINT15.
Bit 6: PINT1R
Description
0
No interrupt request input to pins PINT8 to PINT15
(Initial value)
1
Interrupt request input to pins PINT8 to PINT15
Bit 5—IRQ5 Interrupt Request (IRQ5R): Indicates whether there is interrupt request input to
the IRQ5 pin. When edge detection mode is set for IRQ5, an interrupt request is cleared by
clearing the IRQ5R bit.
Bit 5: IRQ5R
Description
0
No interrupt request input to IRQ5 pin
(Initial value)
1
Interrupt request input to IRQ5 pin
Summary of Contents for SH7709S
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