196
8.6
Timing of STATUS Pin Changes
The timing of STATUS1 and STATUS0 pin changes is shown in figures 8.1 through 8.8.
8.6.1
Timing for Resets
Power-On Reset
CKIO, CKIO2
*
4
RESETP
STATUS
Normal
*
2
Normal
*
2
Reset
*
1
PLL settling
time
0 to 5 Bcyc
*
3
0 to 30 Bcyc
*
3
RESETOUT
Notes:
*
1 Reset:
HH (STATUS1 high, STATUS0 high)
*
2 Normal:
LL (STATUS1 low, STATUS0 low)
*
3 Bcyc:
Bus clock cycle
*
4 The CKIO2 output is available only in clock modes 0, 1, and 2.
Figure 8.2 Power-On Reset (Clock Modes 0, 1, 2, and 7) STATUS Output
Summary of Contents for SH7709S
Page 2: ...Hitachi SuperH RISC engine SH7709S Hardware Manual ADE 602 250 Rev 1 0 09 21 01 Hitachi Ltd ...
Page 75: ...56 ...
Page 107: ...88 ...
Page 125: ...106 ...
Page 139: ...120 ...
Page 203: ...184 ...
Page 245: ...226 ...
Page 411: ...392 ...
Page 609: ...590 ...
Page 635: ...616 ...
Page 663: ...644 ...
Page 679: ...660 ...