Check the setup/hold with single clock, multiple clock edges
1
Select the logic analyzer setup/hold time.
a
In the logic analyzer Format menu, select Master Clock.
b
Select and activate any multiple clock edge.
c
Select the Setup/Hold field, then select the setup/hold to be tested for all pods. The
first time through this test, use the top combination in the following table.
Setup/Hold Combinations
3.5/0.0 ns
-0.5/4.0 ns
d
Select Done to exit the setup/hold combinations.
Testing Performance
To test the single-clock, multiple-edge, state acquisition (logic analyzer)
3–49
Summary of Contents for 1670G Series
Page 20: ...1 12...
Page 116: ...Testing Performance Performance Test Record pattern generator 3 92...
Page 126: ...Calibrating and Adjusting To test the CAL OUTPUT ports 4 10...
Page 166: ...Exploded View of the Agilent 1670G series logic analyzer Replacing Assemblies 6 4...
Page 201: ...Theory of Operation The Oscilloscope Board 8 11...
