6-33
IM 701240-01E
3
2
1
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
App
Index
Triggering
Condition B (Set Pattern)
Pattern of each channel: CH1 to CH16, Logic A, and Logic B
Select from the following:
• CH1 to CH16 (Other Than Logic Inputs)
H: Above the preset trigger level
L:
Below the preset trigger level
X:
Don’t Care
• Logic Input
Enable:
Make the combination of the pattern
1
of each bit the trigger condition
Disable: Don’t Care
1 Select the pattern of each pattern from the following:
H:
Above a certain level
2
L:
Below a certain level
2
X:
Don’t Care
2 Varies depending on the logic probe being used as follows:
702911/702912/700986: Approx. 1.4 V
700987:
6 V
±
50% (for DC input)
700987:
50 V
±
50% (for AC input)
Pulse Width (Time)
0.1
µ
s to 10 s (resolution : 0.1
µ
s)
Notes for Setting the B>Time, B<Time, or B Time Out Trigger
Correct operation is not guaranteed if adjacent pulses are less than 0.1
µ
s apart or if the
pulse width is less than 0.1
µ
s (typical).
0.1
µ
s or more
Trigger Level
The trigger level setting applies to both simple and enhanced triggers.
See “Trigger Level” in section 6.5.
Trigger Hysteresis
Sets a width to the trigger level so that triggers are not activated by small changes in the
trigger signal. Select the trigger hysteresis from
,
, and
.
See “Trigger Hysteresis” in section 6.5.
Hold Off
See section 6.4.
6.14 Setting the B > Time, B < Time, or B Timeout (Pulse Width) Trigger (ENHANCED)
