Toshiba TX49 TMPR4937, Руководство пользователя

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Chapter 21 Electrical Characteristics
21-6
21.5.3 SDRAM Interface AC characteristics
(Tc = 0 – 70
°
C, VCCIO = 3.3 V
±
0.2 V, VCCInt = 1.5 V
±
0.1 V, VSS = 0 V, CL = 150 pF)
Item Symbol Conditions Min. Max. Unit
SDCLK[3:0] Cycle Time t
CYC_SDCLK
C
L
=50 pF, 16 mA buffer time 7.5
⎯
ns
SDCLK[3:0] High Time t
HIGH_SDCLK
C
L
=50 pF, 16 mA buffer time 2.5
⎯
ns
SDCLK[3:0] Low Time t
LOW_SDCLK
C
L
=50 pF, 16 mA buffer time 2.5
⎯
ns
SDCLKIN Input Skew t
BP
When in the Non-bypass mode
* 4)
0
t
CYC_SDCLK
– 5.5
ns
C
L
=150 pF, 16 mA buffer, * 1) 1.5 6.5 ns
ADDR[19:5] Output Delay t
VAL_ADDR1
C
L
= 80 pF, 16 mA buffer,
*
1) 1.5 5.2 ns
SDCS[3:0] * Output Delay t
VAL_SDCS
C
L
= 80 pF, 16 mA buffer 1.5 5.2 ns
C
L
=150 pF, 16 mA buffer, * 1) 1.5 6.5 ns
RAS * Output Delay t
VAL_RAS
C
L
= 80 pF, 16 mA buffer, * 1) 1.5 5.2 ns
C
L
=150 pF, 16 mA buffer, * 3) 1.5 6.5 ns
CAS * Output Delay t
VAL_CAS
C
L
= 80 pF, 16 mA buffer, * 3) 1.5 5.2 ns
C
L
=150 pF, 16 mA buffer,
*
3) 1.5 6.5 ns
WE * Output Delay t
VAL_WE
C
L
= 80 pF, 16 mA buffer, * 3) 1.5 5.2 ns
C
L
=150 pF, 16 mA buffer 1.5 6.5 ns
CKE Output Delay t
VAL_CKE
C
L
= 80 pF, 16 mA buffer 1.5 5.2 ns
C
L
= 50 pF, 16 mA buffer,
*
2) 1.5 6.5 ns
DQM[7:0] Output Delay t
VAL_DQM
C
L
= 30 pF, 16 mA buffer, * 2) 1.5 5.2 ns
C
L
= 50 pF, 16 mA buffer,
*
2) 1.5 6.5 ns
DATA[63:0] Output Delay (H
→
L, L
→
H) t
VAL_DATA1
C
L
= 30 pF, 16 mA buffer, * 2) 1.5 5.2 ns
C
L
= 50 pF, 16 mA buffer, * 2) 1.5 6.5 ns
DATA[63:0] Output Delay (Valid
→
Hi-
Z)
t
VAL_DATA1ZV
C
L
= 30 pF, 16 mA buffer,
*
2) 1.5 5.2 ns
C
L
= 50 pF, 16 mA buffer, * 2) 1.5 6.5 ns
DATA[63:0] Output Delay (Valid
→
Hi-Z) t
VAL_DATA1VZ
C
L
= 30 pF, 16 mA buffer, * 2) 1.5 5.2 ns
DATA[63:0] Input Setup Time t
SU_DATA1B
When in the Bypass mode 4.0
⎯
ns
DATA[63:0] Input Hold Time t
HO_DATA1B
When in the Bypass mode 0.5
⎯
ns
DATA[63:0] Input Setup Time t
SU_DATA1NB
When in the Non-bypass mode 1.0
⎯
ns
DATA[63:0] Input Hold Time t
HO_DATA1NB
When in the Non bypass mode 1.0
⎯
ns
*
1) Becomes a 2-cycle signal when tDACT of SDCTR1 is “1”.
*
2) Becomes a 2-cycle signal when tSWB of SDCTR1 is “1”.
* 3) 2-cycle signal
For information on 2-cycle operation, see the description in Chapter 9 SDRAM Controller.
* 4) The MAX value is is t
CYC_SDCLK
– 5.5 ns.
Figure 21.5.3 Timing Diagram: Output Signal and Input Signal when in the Bypass Mode
(SDCLK Reference)
t
VAL_ *
SDCLK[n]
OUTPUT
INPUT
t
HO_ *
t
SU_ *
outputs valid
inputs valid