Toshiba TX49 TMPR4937, Руководство пользователя

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Chapter 10 PCI Controller
10-13
Initial state operation matches the correspondence between the address and byte data regardless of the
endian mode (operation is address consistent). For example, if WORD (16-bit) data is written to address
0 of the PCI Bus when the TX4937 is in the Big Endian mode, the upper byte (address 0 in Big Endian)
is written to PCI Bus address 0 and the lower byte (address 1 in Big Endian) is written to address 1 of
the PCI Bus. For Little Endian PCI devices, this means that the byte order is reversed.
When in the Big Endian mode and a particular access window Endian switching mechanism is
validated, data is transferred so the byte order does not change in DWORD (32-bit) access to that access
window.
Endian switching during initiator access is specified by the Byte Swap bit (BSWAP) of the G-Bus
Base Address Register (G2PMnGBASE, G2PIOGBASE) of the access window for each initiator access
(see Table 10.3.3).
Ending switching during target access is specified by the Byte Swap bit (BSWAP) of the G-Bus Base
Address Register (P2GMnGBASE, P2GIOGBASE) of the access window for each target access (see
Table 10.3.5).
10.3.8 66 MHz Operation Mode
The TX4937 PCI Controller supports 66 MHz PCI. When in the Host mode, the procedure for setting
the PCI Bus to the 66 MHz mode is as follows below.
(1) Start the system with a PCI Bus Clock frequency of 33 MHz or less.
(2) The TX4937 system initialization program checks the 66 MHz Capable bit (bit 5) of the
configuration Space Register Status Register in all PCI devices. If the 66 MHz Capable bit of all
devices is set, then change the PCI Bus Clock frequency according to the following procedure.
(3) Assert the PCI Bus Reset signal. (The TX4937 does not have PCI Reset output, so it is necessary to
use an external circuit to control the PCI Bus Reset signal.)
(4) Set the Software Reset bit (PCICFG.SRST) of the PCI Controller Configuration Register.
(5) Setting the PCI66 MHz Mode bit (CCFG.PCI66) of the Chip Configuration Register asserts the
M66EN signal.
(6) Modifying the setting of the PCICLK Division Ratio field (CCFG.PCIDIVMODE) of the Chip
Configuration Register changes the PCI Clock frequency from 33 MHz to 66 MHz.
(7) The software reset bit (PCICCFG.SRST) is cleared after the PLL stabilizes (about 10 ms).
(8) Deassert the PCI Bus Reset signal. Each PCI device detects assertion of the M66EN signal if
necessary and performs the process.
When the TX4937 is in the Satellite mode, the M66EN signal becomes the input signal. It is possible
to read this state from the 66 MHz Drive Status bit (P2GSTATUS.M66EN) of the P2G Status Register.