Toshiba TX49 TMPR4937, Руководство пользователя

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Chapter 7 External Bus Controller
7-16
7.3.7.4 ACK * Input Timing (External ACK Mode)
The ACK* signal becomes an input signal when in the external ACK mode.
During a Read cycle, data is latched two clock cycles after assertion of the ACK* signal is
acknowledged (Figure 7.3.9 ACK* Input Timing (Single Read Cycle)). During a Write cycle,
assertion of the ACK* signal is acknowledged, SWE*/BWE* is deasserted three clock cycles
later, then data is held for one clock cycle after that (Figure 7.3.10 ACK* Input Timing (Single
Write Cycle).
The ACK* input signal is internally synchronized. Due to internal State Machine restrictions,
ACK* cannot be acknowledged consecutively on consecutive clock cycles. External devices can
assert ACK* across multiple clock cycles under the following conditions.
•
During Single access, the ACK* signal can be asserted before the end of the cycle during
which CE* is dasserted.
•
During Burst access, it is possible to assert the ACK* signal for up to three clock cycles
during Reads and for up to five clock cycles during Writes. If the ACK* signal is asserted for
a period longer than this, it will be acknowledged as the next valid ACK* signal.
Figure 7.3.9 ACK * Input Timing (Single Read Cycle)
Figure 7.3.10 ACK * Input Timing (Single Write Cycle)
SYSCLK
CE
*
ADDR [19 : 0]
OE *
DATA [31 : 0]
ACK * /READY (Input)
Latch Data
Acknowledge ACK *
2 clocks
EBCCRn.SHWT=0
SYSCLK
CE *
ADDR [19:0]
SWE */ BWE *
DATA [31:0]
ACK
*
/READY (Input)
3 clocks
4 clocks
Acknowledge ACK *
EBCCRn.SHWT=0