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Chapter 9 SDRAM Controller
9-25
9.4.5
ECC Status Register (ECCSR)
0xA008
63
48
ERRAD
R
:Type
— — — — — — — — — — — — — — — —
:Initial
value
47
32
ERRAD
R
:Type
— — — — — — — — — — — — — — — —
:Initial
value
31 28 27 26 24 23 22 21 20 16
ERRAD
Reserved
ERRMODE
Reserved
ERRMW
Reserved
R
R
R
:Type
— — — — — — — — — —
:Initial
value
15 8 7 2 1 0
ERRS Reserved
MBERR SBERR
R
R/W
R/W
:Type
— — — — — — — — 0 0
:Initial
value
Bit Mnemonic Field
Name
Description
Read/Write
63:28
ERRAD
Error Address
Error Address (Default: Unknown)
A 36-bit physical address is set when an error occurs. This address is
retained until either SBERR or MBERR is cleared. This field is Read Only.
R
27 —
— Reserved
⎯
26:24 ERRMODE Error ECC/Parity
Mode
Error ECC Mode (Default: Unknown)
The ECC/Parity Mode is set when an error occurs. This address is retained
until either SBERR or MBERR is cleared. This field is Read Only.
R
23:22 —
— Reserved
⎯
21 ERRMW
Error Memory
Width
Error Memory Width (Default: Unknown)
The memory data width is set when an error occurs. This address is
retained until either SBERR or MBERR is cleared. This field is Read Only.
0: 64 bits
1: 32 bits
R
20:16 —
— Reserved
⎯
15:8
ERRS
Error Syndrome
Error Syndrome (Default: Unknown)
The error syndrome for when errors occur is set. The syndrome is retained
until either SBERR or MBERR is cleared. This field is Read Only.
R
7:2 —
— Reserved
⎯
1
MBERR
Multi-Bit Error
Multi-Bit Error (Default: 0)
This bit is set to “1” when a multi-bit error occurs, or when a parity error
occurs while in the Parity Mode. Once a multi-bit error occurs, until this bit
is cleared, no status in the Status Register is updated even if new multi-
/single-bit errors occur.
0: No error
1: Generate error
R/W
0
SBERR
Single-Bit Error
Single-Bit Error (Default: 0)
This bit is set to “1” when a single-bit error occurs. Once a single-bit error
occurs, until this bit is cleared, no status in the Status Register is updated
even if new single-bit error occurs. If a multi-bit error occurs, status is
updated regardless of whether a single-bit error has occurred or not.
0: No error
1: Generate error
R/W
Figure 9.4.5 ECC Status Register
Содержание TX49 TMPR4937
Страница 1: ...64 Bit TX System RISC TX49 Family TMPR4937 Rev 2 0 ...
Страница 4: ......
Страница 13: ...Table of Contents ix TMPR4937 Revision History 1 ...
Страница 14: ...Table of Contents x ...
Страница 15: ...Handling Precautions ...
Страница 16: ......
Страница 18: ...1 Using Toshiba Semiconductors Safely 1 2 ...
Страница 40: ...3 General Safety Precautions and Usage Considerations 3 18 ...
Страница 42: ...4 Precautions and Usage Considerations 4 2 ...
Страница 43: ...TMPR4937 2005 3 Rev 2 0 ...
Страница 44: ......
Страница 52: ...Chapter 1 Overview and Features 1 6 ...
Страница 156: ...Chapter 7 External Bus Controller 7 56 ...
Страница 491: ...Chapter 16 Removed 16 1 16 Removed ...
Страница 492: ...Chapter 16 Removed 16 2 ...
Страница 493: ...Chapter 17 Removed 17 1 17 Removed ...
Страница 494: ...Chapter 17 Removed 17 2 ...
Страница 495: ...Chapter 18 Removed 18 1 18 Removed ...
Страница 496: ...Chapter 18 Removed 18 2 ...
Страница 497: ...Chapter 19 Removed 19 1 19 Removed ...
Страница 498: ...Chapter 19 Removed 19 2 ...
Страница 506: ...Chapter 20 Extended EJTAG Interface 20 8 ...
Страница 529: ...Chapter 22 Pinout and Package Information 22 9 22 2 Package Dimensions P BGA484 3535 1 27B9 Unit mm ...
Страница 530: ...Chapter 22 Pinout and Package Information 22 10 ...
Страница 542: ...Chapter 24 Parts Number when Ordering 24 2 ...
Страница 544: ...Appendix A TX49 H3 Core Supplement A 2 ...