Toshiba TX49 TMPR4937, Руководство пользователя

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Chapter 7 External Bus Controller
7-6
7.3.4 External Address Output
The maximum memory space size for each channel is 1 GB (230B). Addresses are output by dividing
the 20-bit ADDR[19:0] signal into two parts: the upper address and the lower address. The address bit
output to each bit of the ADDR[19:0] signal changes according to the setting of the channel data bus
width. (See “7.3.5 Data Bus Size” for more information.)
It is possible for an external device to latch the upper eight address bits using the ACE* signal. Either
the ACE* signal itself can be used as a Latch Enable signal or the upper address can be latched at the
rise of SYSCLK when the ACE* signal is being asserted.
The ADDR signal output is held for one clock cycle after the ACE* signal rise when the
CCFG.ACEHOLD bit is set (default). (See Figure 7.5.1.) The ADDR signal output is not held when the
CCFG.ACEHOLD bit is cleared. This hold time setting is applied globally to all channels.
The ACE* signal of the upper address is always asserted at the first external bus access cycle after
Reset. In all subsequent external bus access cycles, the bit mapping of the upper address output to
ADDR[19:12] is compared to the bit mapping of the upper address output to ADDR[19:12] previously.
The upper address is output and the ACE* signal is asserted only if the compared results do not match.
As indicated below in Table 7.3.3, in the case of channel sizes that do not use the upper address
latched by the ACE* signal, with the exception of the first cycle after reset, the upper address is not
output and the ACE* signal is not asserted.
Table 7.3.3 Relationship Between the Upper Address Output and the Channel Size (CS)
CS
Bus Width
1 MB 2 MB 4 MB 8 MB or more
32 bits
⎯ ⎯ ⎯
√
16 bits
⎯ ⎯ √
√
8 bits
⎯ √ √
√
√
: The upper address output changes when the upper address changes.
⎯
: The upper address output does not change (with the exception of the first cycle after
reset.)