Intel
®
IXP45X and Intel
®
IXP46X Product Line of Network Processors
August 2006
Developer’s Manual
Order Number: 306262-004US
863
Synchronous Serial Port—Intel
®
IXP45X and Intel
®
IXP46X Product Line of Network Processors
Each buffer consists of a dual-port register file with control circuitry to make it work as
a FIFO, with independent read and write ports.
Buffer filling and emptying may be performed by the system processor in response to
an interrupt from the FIFO logic. Each FIFO has a programmable threshold at which an
interrupt is triggered. When the threshold value is exceeded, an interrupt is generated
which, if enabled, signals the host processor to empty an “inbound” FIFO or to refill an
“outbound” FIFO.
The system can also poll status bits to learn how full a FIFO is.
20.4
Baud-Rate Generation
The baud (or bit-rate clock) is generated internally by dividing the standard input clock
(3.6864 MHz), which is first divided by 2. This feeds a programmable divider to
generate baud rates from 7.2 KHz to 1.8432 Mbps. Optionally, an external clock
(SSP_EXTCLK) can be used to replace the 3.6864 MHz standard input clock.
20.5
SSP Serial Port Registers
There are five registers in the SSP block: two control, one data, one status register, and
one test register.
• Control registers are used to program the baud rate, data length, frame format,
data transfer mechanism, and port enabling. In addition, they permit setting the
FIFO “fullness” threshold that will trigger an interrupt.
• The Data Register is mapped as one 32-bit location, which physically points to
either of two 32-bit registers. One register is for WRITES, and transfers data to the
Transmit FIFO; the other is for READS, and takes data from the Receive FIFO. A
write cycle will load successive words into the SSP Write Register, from the lower
half 2 bytes of a 32-bit word to the Transmit FIFO. A READ cycle will similarly take
data from the SSP Read Register, and the Receive FIFO will reload it with available
data bits it has stored.
Read and writes should not increment the address; all accesses to the SSP Data
Register memory address will access the Read or Write Register.
The FIFOs are independent buffers that allow full duplex operation.
• The Status Register signals the state of the FIFO buffers: whether the
programmable threshold has been passed (Transmit/Receive Buffer service
request), and a value showing the actual “fullness” of the FIFO. There are flag bits
to indicate when the SSP is actively transmitting data, when the Transmit Buffer is
not full, and when the Receive Buffer is not empty. Error bits signal overrun errors.
Table 273.
SSP Serial Port Register Summary
Block
Address
Register Name
Description
Reset Value
Page
Number
