Intel ITANIUM ARCHITECTURE - SOFTWARE DEVELOPERS VOLUME 3 REV 2.3, Руководство пользователя

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Volume 2, Part 1: System State and Programming Model 2:31
3.3.4 Global Control Registers
3.3.4.1 Default Control Register (DCR – CR0)
The DCR specifies default parameters for PSR values on interruption, some additional
global controls, and whether speculative load faults can be deferred.
Figure 3-3 and
Table 3-5 define and describe the DCR fields.
srlz.i, rfi
Serialize instruction references Ensure side effects are observed by
the instruction fetch stream M
srlz.d
Serialize data references Ensure side effects are observed by
the execute and data streams M
Figure 3-3. Default Control Register (DCR – CR0)
63 15 14 13 12 11 10 9 8 7 3 2 1 0
rv dd da dr dx dk dp dm rv lc be pp
49 1 1 1 1 1 1 1 5 1 1 1
Table 3-5. Default Control Register Fields
Field Bit Description
Serialization
Required
pp 0 Privileged Performance monitor default – On interruption, DCR.pp is
loaded into PSR.pp. data
be 1 Big-Endian default – When 1, Virtual Hash Page Table (VHPT) walker
accesses are performed big-endian; otherwise, little-endian. On
interruption, DCR.be is loaded into PSR.be. inst
lc 2 IA-32 Lock Check enable – When 1, and an IA-32 atomic memory
reference is defined as requiring a read-modify-write operation external to
the processor under an external bus lock, an IA_32_Intercept(Lock) is
raised. (IA-32 atomic memory references are defined to require an
external bus lock for atomicity when the memory transaction is made to
non-write-back memory or are unaligned across an
implementation-specific non-supported alignment boundary.) When 0,
and an IA-32 atomic memory reference is defined as requiring a
read-modify-write operation external to the processor under external bus
lock, the processor may either execute the transaction as a series of
non-atomic transactions or perform the transaction with an external bus
lock, depending on the processor implementation. Intel Itanium
semaphore accesses ignore this bit. All unaligned Intel Itanium
semaphore references generate an Unaligned Data Reference fault. All
aligned Intel Itanium semaphore references made to memory that is
neither write-back cacheable nor a NaTPage result in an Unsupported
Data Reference fault. data
dm 8 Defer TLB Miss faults only (VHPT data, Data TLB, and Alternate Data
TLB faults) – When 1, and a TLB miss is deferred, lower priority Debug
faults may still be delivered. A TLB miss fault, deferred or not, precludes
concurrent Page not Present, Key Miss, Key Permission, Access Rights,
or Access Bit faults. This bit is ignored by IA-32 instructions. data
dp 9 Defer Page not Present faults only – When 1, and a Page not Present
fault is deferred, lower priority Debug faults may still be delivered. A Page
not Present fault, deferred or not, precludes concurrent Key Miss, Key
Permission, Access Rights, or Access Bit faults. This bit is ignored by
IA-32 instructions. data
Table 3-4. Control Register Instructions (Continued)
Mnemonic Description Operation Format