Volume 2, Part 1: Processor Abstraction Layer
2:411
PAL_MC_ERROR_INFO
All other values of
info_index
are reserved. When
info_index
is equal to 0 or 1, the
level_index
and
err_type_index
input values are ignored. When
info_index
is equal to
2, the
level_index
and
err_type_index
define the format of the
error_info
return value.
The caller is expected to first make this procedure call with
info_index
equal to zero to
obtain the processor error map. This error map informs the caller about the processor
core identification, the processor thread identification and indicates which structure(s)
caused the machine check. If more than one structure generated a machine check,
multiple structure bits will be set. The caller then uses this information to make
sub-sequent calls to this procedure for each structure identified in the processor error
map to obtain detailed error information.
The
level_index
input argument specifies which processor core, processor thread and
structure for which information is being requested. See
the definition of the
level_index
fields. This procedure call can only return information
about one processor structure at a time. The caller is responsible for ensuring that only
one structure bit in the l
evel_index
input argument is set at a time when retrieving
information, otherwise the call will return that an invalid argument was passed.
Table 11-86.
info_index
Values
info_index
Error Information Type
Description
0
Processor Error Map
This
info_index
value will return the processor
error map. This return value specifies the
processor core identification, the processor
thread identification, and a bit-map indicating
which structure(s) of the processor generated the
machine check. This bit-map has the same layout
as the
level_index
. A one in the structure bit-map
indicates that there is error information available
for the structure. The layout of the
level_index
is
described in
Figure 11-19, “level_index Layout”
.
1
Processor State Parameter
This
info_index
value will return the same
processor state parameter that is passed at the
PALE_CHECK exit state for a machine check
event (provided a valid min-state save area has
been registered) or will construct a processor
state parameter for a corrected machine check
events. This parameter describes the severity of
the error and the validity of the processor state
when the machine check or CMCI occurred. This
procedure will not return a valid PSP for INIT
events. The Processor State Parameter is
described in
Figure 11-11, “Processor State
.
2
Structure-specific Error Information
This
info_index
value will return error information
specific to a processor structure. The structure is
specified by the caller using the
level_index
and
err_type_index
input parameters. The value
returned in
error_info
is specific to the structure
and type of information requested.
Figure 11-19.
level_index
Layout
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9
8
7
6
5
4
3
2
1
0
erf
ebh
edt
eit
edc
eic
tid
cid
63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32
Содержание ITANIUM ARCHITECTURE - SOFTWARE DEVELOPERS VOLUME 3 REV 2.3
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Страница 149: ...1 138 Volume 1 Part 2 About the Optimization Guide ...
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Страница 264: ...2 16 Volume 2 Part 1 Intel Itanium System Environment ...
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Страница 486: ...2 238 Volume 2 Part 1 IA 32 Interruption Vector Descriptions ...
Страница 749: ...2 501 Intel Itanium Architecture Software Developer s Manual Rev 2 3 Part II System Programmer s Guide ...
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Страница 754: ...2 506 Volume 2 Part 2 About the System Programmer s Guide ...
Страница 796: ...2 548 Volume 2 Part 2 Interruptions and Serialization ...
Страница 808: ...2 560 Volume 2 Part 2 Context Management ...
Страница 842: ...2 594 Volume 2 Part 2 Floating point System Software ...
Страница 850: ...2 602 Volume 2 Part 2 IA 32 Application Support ...
Страница 862: ...2 614 Volume 2 Part 2 External Interrupt Architecture ...
Страница 870: ...2 622 Volume 2 Part 2 Performance Monitoring Support ...
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Страница 941: ...3 42 Volume 3 Instruction Reference cmp illegal_operation_fault PR p1 0 PR p2 0 Interruptions Illegal Operation fault ...
Страница 1099: ...3 200 Volume 3 Instruction Reference padd Interruptions Illegal Operation fault ...
Страница 1191: ...3 292 Volume 3 Pseudo Code Functions Intel Itanium Architecture Software Developer s Manual Rev 2 3 ...
Страница 1295: ...3 396 Volume 3 Resource and Dependency Semantics ...
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Страница 1302: ...402 Intel Itanium Architecture Software Developer s Manual Rev 2 3 ...
Страница 1494: ...4 192 Volume 4 Base IA 32 Instruction Reference FWAIT Wait See entry for WAIT ...
Страница 1564: ...4 262 Volume 4 Base IA 32 Instruction Reference LES Load Full Pointer See entry for LDS LES LFS LGS LSS ...
Страница 1565: ...Volume 4 Base IA 32 Instruction Reference 4 263 LFS Load Full Pointer See entry for LDS LES LFS LGS LSS ...
Страница 1568: ...4 266 Volume 4 Base IA 32 Instruction Reference LGS Load Full Pointer See entry for LDS LES LFS LGS LSS ...
Страница 1583: ...Volume 4 Base IA 32 Instruction Reference 4 281 LSS Load Full Pointer See entry for LDS LES LFS LGS LSS ...
Страница 1647: ...Volume 4 Base IA 32 Instruction Reference 4 345 ROL ROR Rotate See entry for RCL RCR ROL ROR ...
Страница 1663: ...Volume 4 Base IA 32 Instruction Reference 4 361 SHL SHR Shift Instructions See entry for SAL SAR SHL SHR ...
Страница 1668: ...4 366 Volume 4 Base IA 32 Instruction Reference SIDT Store Interrupt Descriptor Table Register See entry for SGDT SIDT ...
Страница 1884: ...4 582 Volume 4 IA 32 SSE Instruction Reference ...
Страница 1885: ...Index Intel Itanium Architecture Software Developer s Manual Rev 2 3 Index ...
Страница 1886: ...Index Intel Itanium Architecture Software Developer s Manual Rev 2 3 ...
Страница 1898: ...INDEX Index 12 Index for Volumes 1 2 3 and 4 ...