Intel ITANIUM ARCHITECTURE - SOFTWARE DEVELOPERS VOLUME 3 REV 2.3, Руководство пользователя

Страница: 817 / 1898

Volume 2, Part 2: Memory Management 2:569
A data or instruction serialization operation must be performed after the
ptc.l
before
the translation is guaranteed to be no longer visible to the local data or instruction
stream, respectively.
The
ptc.l
instruction does not modify the page tables nor any other memory location,
nor does it affect the TLB state of any processor other than the one on which it is
executed.
The
ptc.l
instruction ensures that all prior stores are made locally visible before the
actual purge operation is performed. Consider the following code sequence:
st8 [VHPT] = <new_translation>
ptc.l <old_translation>
srlz.i
The
ptc.l
instruction will purge the translation only after the local store update is seen.
If there was a hardware-initiated VHPT walk for the same translation, it would either
insert the
old_translation
in the TLB before the
ptc.l
executes and then get purged by
the
ptc.l
, or insert the
new_translation
after both the local store update and
ptc.l
purge are complete.
5.2.2.2.2 ptc.e
To purge all TC entries from the local processor’s TLBs, software uses a series of
ptc.e
instructions. Software must call the PAL_PTCE_INFO PAL routine at boot time to
determine the parameters needed to use the
ptc.e
instruction. Specifically,
PAL_PTCE_INFO returns:
• tc_base – an unsigned 64-bit integer denoting the beginning address to be used by
the first
ptc.e
instruction in the purge loop.
• tc_counts – two unsigned 32-bit integers packed into a 64-bit parameter denoting
the loop counts of the outer and inner purge loops. count1 (outer loop) is contained
in bits {63:32} of the parameter, and count2 (inner loop) is contained in bits
{31:0} of the parameter.
• tc_strides – two unsigned 32-bit integers packed into a 64-bit parameter denoting
the loop stride of the outer and inner purge loops. stride1 (outer loop) is contained
in bits {63:32} of the parameter, and stride2 (inner loop) is contained in bits
{31:0} of the parameter.
Software then executes the following sequence:
disable_interrupts();
addr = tc_base;
for (i = 0; i < count1; i++) {
for (j = 0; j < count2; j++) {
ptc.e addr;
addr += stride2;
}
addr += stride1;
}
enable_interrupts();
A data or instruction serialization operation must be performed after the sequence
shown above before the translations are guaranteed to be no longer visible to the local
data or instruction stream, respectively.
The
ptc.e
instruction does not modify the page tables nor any other memory location,
nor does it affect the TLB state of any processor other than the one on which it is
executed.