Intel ITANIUM ARCHITECTURE - SOFTWARE DEVELOPERS VOLUME 3 REV 2.3, Руководство пользователя

Страница: 1384 / 1898

4:82 Volume 4: Base IA-32 Instruction Reference
When the input value is 2, the processor returns information about the processor’s
internal caches and TLBs in the EAX, EBX, ECX, and EDX registers. The encoding of
these registers is as follows:
• The least-significant byte in register EAX (register AL) indicates the number of
times the CPUID instruction must be executed with an input value of 2 to get a
complete description of the processor’s caches and TLBs.
• The most significant bit (bit 31) of each register indicates whether the register
contains valid information (set to 0) or is reserved (set to 1).
• If a register contains valid information, the information is contained in 1 byte
descriptors.
Please see the processor-specific supplement for further information on how to decode
the return values for the processors internal caches and TLBs.
CPUID performs instruction serialization and a memory fence operation.
22 ACPI Thermal Monitor and Software Controlled Clock Facilities. The
processor implements internal MSRs that allow processor
temperature to be monitored and processor performance to be
modulated in predefined duty cycles under software control.
23 MMX Intel MMX Technology. The processor supports the Intel MMX
technology.
24 FXSR FXSAVE and FXRSTOR Instructions. The FXSAVE and FXRSTOR
instructions are supported for fast save and restore of the floating
point context. Presence of this bit also indicates that CR4.OSFXSR is
available for an operating system to indicate that it supports the
FXSAVE and FXRSTOR instructions
25 SSE SSE. The processor supports the SSE extensions.
26 SSE2 SSE2. The processor supports the SSE2 extensions.
27 SS Self Snoop. The processor supports the management of conflicting
memory types by performing a snoop of its own cache structure for
transactions issued to the bus.
28 HTT Hyper-Threading Technology. The processor implements
Hyper-Threading technology.
29 TM Thermal Monitor. The processor implements the thermal monitor
automatic thermal control circuitry (TCC).
30 Processor based on the Intel
Itanium architecture
The processor is based on the Intel Itanium architecture and is
capable of executing the Intel Itanium instruction set. IA-32 application
level software MUST also check with the running operating system to
see if the system can also support Itanium
architecture-based code
before switching to the Intel Itanium instruction set.
31 PBE Pending Break Enable. The processor supports the use of the
FERR#/PBE# pin when the processor is in the stop-clock state
(STPCLK# is asserted) to signal the processor that an interrupt is
pending and that the processor should return to normal operation to
handle the interrupt. Bit 10 (PBE enable) in the IA32_MISC_ENABLE
MSR enables this capability.
Table 2-5. Feature Flags Returned in EDX Register (Continued)
Bit Mnemonic Description