Intel ITANIUM ARCHITECTURE - SOFTWARE DEVELOPERS VOLUME 3 REV 2.3, Руководство пользователя

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1:198 Volume 1, Part 2: Software Pipelining and Loop Support
5.5.6 Loop Unrolling Prior to Software Pipelining
In some cases, higher performance can be achieved by unrolling the loop prior to
software pipelining. Loops that are resource constrained can be improved by unrolling
such that the limiting resource is more fully utilized. In the following example if we
assume the target processor has only two memory units, the loop performance is
bound by the number of memory units:
L1: ld4 r4 = [r5],4 // Cycle 0
ld4 r9 = [r8],4;; // Cycle 0
add r7 = r4,r9;; // Cycle 2
st4 [r6] = r7,4 // Cycle 3
br.cloop L1;; // Cycle 3
A pipelined version of this loop must have an II of at least two because there are three
memory instructions, but only two memory units. If the loop is unrolled twice prior to
software pipelining and assuming the store is independent of the loads, an II of 3 can
be achieved for the new loop. This is an effective II of 1.5 for the original source loop.
Below is a possible pipeline for the unrolled loop:
stage 1:
(p16)
ld4 r4 = [r5],8 // odd iteration
(p16) ld4 r9 = [r8],8;; // odd iteration
stage 2:
(p16)
ld4 r14 = [r15],8 // even iteration
(p16) ld4 r19 = [r18],8;; // even iteration
// --- empty cycle
stage 3:(p18) add r7 = r4,r9 // odd iteration
(p17) add r17 = r14,r19;; // even iteration
stage 4: // --- empty cycle
(p19) st4 [r6] = r7,8 // odd iteration
(p18) st4 [r16] = r17,8;; // even iteration
The unrolled loop contains two copies of the source loop body, one that corresponds to
the odd source iterations and one that corresponds to the even source iterations. The
assignment of stage predicates must take this into account. Recall that each one
written to
p16
sequentially enables all the stages for a new source iteration. During
stage one of the above pipeline, the stage predicate for the odd iteration is in
p16
. The
stage predicate for the even iteration does not exist yet. During stage two of the above
pipeline, the stage predicate for the odd iteration is in
p17
and the new stage predicate
for the even iteration is in
p16
. Thus within the same pipeline stage, if the stage