Intel ITANIUM ARCHITECTURE - SOFTWARE DEVELOPERS VOLUME 3 REV 2.3, Руководство пользователя

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2:580 Volume 2, Part 2: Runtime Support for Control and Data Speculation
Details on these three models are discussed in the next three sections as well as in
Section 5.5.5, “Deferral of Speculative Load Faults” on page 2:105 .
6.1.1 Hardware-only Deferral
Hardware only deferral is configured by setting all speculation deferral bits in the DCR
register (dd, da, dr, dx, dk, dp and dm) to 1. All excepting control speculative loads are
automatically deferred by the processor. As a result, all excepting control speculative
loads that hit non-fatal exceptions, e.g. a TLB miss or a page fault, will be deferred by
the processor hardware, and will cause speculation recovery code to be invoked. This
can cause speculation recovery code to be invoked more often than strictly necessary.
6.1.2 Combined Hardware/Software Deferral
Setting of a DCR deferral bit to 1 results in hardware deferral by the processor, whereas
clearing of a deferral bit causes exceptions to be delivered to software. The operating
system may want to configure the processor to deliver control speculative exceptions to
its handlers for certain non-fatal faults such as TLB misses or protection key misses.
Early handling of these exceptions avoids unnecessary invocation of speculation
recovery code, and the associated performance penalty. This is especially useful for
exceptions handlers whose overhead is small. Note that handlers will also be invoked
for excepting control speculative loads that have been hoisted from not taken paths,
and therefore are not needed. As a result, software handling of control speculative
exceptions is recommended only for statistically infrequent light weight fault handlers
such as TLB miss or protection key miss handlers. If, while handling the exception, the
operating system determines that this instance of the exception may require too much
effort, e.g. a TLB miss turns out to be a page fault, the handler still has the choice of
software-deferring the exception.
6.1.3 Software-only Deferral
Software only deferral is configured by clearing all speculation deferral bits in the DCR
register (dd, da, dr, dx, dk, dp and dm) to 0. Control speculative loads that hit any
Debug, Access Bit, Access Rights, Key Permissions, Key Miss, or Not Present fault, or
that suffer a TLB miss or a VHPT Translation fault will be delivered to software.
6.2 Speculation Recovery Code Requirements
As described by Table 6-1 , code generators for the Itanium architecture are not always
required to generate speculation recovery code for all forms of speculation. Compilers
and operating systems can collaborate to provide two models for handling of recovery
from failed control speculation:
• ITLB.ed=1 (application with recovery code
–
the default): The compiler generates
appropriate recovery code for all
ld.s
instructions, as well as for
ld.sa
and
ld.a
instructions that have speculatively executed uses. Speculation failure of
ld.sa
and
ld.a
instructions that have no speculatively executed uses can be recovered by a
ld.c
instruction, and hence do not require recovery code. The operating system
may defer non-fatal exceptions.