Intel ITANIUM ARCHITECTURE - SOFTWARE DEVELOPERS VOLUME 3 REV 2.3, Руководство пользователя

Страница: 196 / 1898

Volume 1, Part 2: Software Pipelining and Loop Support 1:185
Itanium architecture allow some loops to be software pipelined without code expansion.
Register rotation provides a renaming mechanism that reduces the need for loop
unrolling and software renaming of registers. Special software pipelined loop branches
support register rotation and, combined with predication, reduce the need to generate
separate blocks of code for the prolog and epilog phases.
5.4.1 Register Rotation
Register rotation renames registers by adding the register number to the value of a
register rename base (rrb) register contained in the CFM. The rrb register is
decremented when certain special software pipelined loop branches are executed at the
end of each kernel iteration. Decrementing the rrb register makes the value in register
X appear to move to register X+1. If X is the highest numbered rotating register, its
value wraps to the lowest numbered rotating register.
A fixed-sized area of the predicate and floating-point register files (
p16
-
p63
and
f32
-
f127
), and a programmable-sized area of the general register file are defined to
rotate. The size of the rotating area in the general register file is determined by an
immediate in the
alloc
instruction and must be either zero or a multiple of 8, up to a
maximum of 96 registers. The lowest numbered rotating register in the general register
file is
r32
. An rrb register is provided for each of the three rotating register files:
CFM.rrb.gr
for the general registers;
CFM.rrb.fr
for the floating-point registers;
CFM.rrb.pr
for the predicate registers. The software pipelined loop branches
decrement all the rrb registers simultaneously.
Below is an example of register rotation. The
swp_branch
pseudo-instruction
represents a software pipelined loop branch:
L1: ld4 r35 = [r4],4 // post increment by 4
st4 [r5] = r37,4 // post increment by 4
swp_branchL1 ;;
The value that the load writes to
r35
is read by the store two kernel iterations (and two
rotations) later as
r37
. In the meantime, two more instances of the load are executed.
Because of register rotation, those instances write their result to different registers and
do not modify the value needed by the store.
The rotation of predicate registers serves two purposes. The first is to avoid
overwriting a predicate value that is still needed. The second purpose is to control the
filling and draining of the pipeline. To do this, a programmer assigns a predicate to each
stage of the software pipeline to control the execution of the instructions in that stage.
This predicate is called the
stage predicate . For counted loops,
p16
is architecturally
defined to be the predicate for the first stage,
p17
is defined to be the predicate for the
second stage, etc. A conceptual view of a pipelined source iteration of the example
counted loop on
page 1:181 is shown below. Each stage is one cycle long and the
stage predicates are shown:
stage 1:(p16) ld4 r4 = [r5],4
stage 2:(p17) --- // empty stage
stage 3:(p18) add r7 = r4,r9
stage 4:(p19) st4 [r6] = r7,4
A register rotation takes place at the end of each stage (when the software-pipelined
loop branch is executed in the kernel loop). Thus a 1 written to
p16
enables the first
stage and then is rotated to
p17
at the end of the first stage to enable the second stage