Intel ITANIUM ARCHITECTURE - SOFTWARE DEVELOPERS VOLUME 3 REV 2.3, Руководство пользователя

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Volume 2, Part 2: MP Coherence and Synchronization 2:509
specific opcode chosen. The
xchg
instruction always has acquire semantics. These
instructions read a value from memory, modify this value using an instruction-specific
operation, and then write the modified value back to memory. The read-modify-write
sequence is atomic by definition.
2.1.3.1 Considerations for using Semaphores
The memory location on which a semaphore instruction operates on must obey two
constraints. First, the location must be cacheable (the
fetchadd
instruction is an
exception to this rule; it may also operate on exported uncacheable locations, UCE).
Thus, with the exception of
fetchadd
to UCE locations, the Itanium architecture does
not support semaphores in uncacheable memory. Second, the location must be
naturally-aligned to the size of the semaphore access. If either of these two constraints
are not met, the processor generates a fault.
The exported uncacheable memory attribute, UCE, allows a processor based on the
Itanium architecture to export fetch and add operations to the platform. A processor
that does not support exported
fetchadd
will fault when executing a
fetchadd
to a UCE
memory location. If the processor supports exported
fetchadd
but the platform does
not, the behavior is undefined when executing a
fetchadd
to a UCE memory location.
Sharing locks between IA-32 and Itanium architecture-based code does work with the
following restrictions:
• Itanium architecture-based code can only manipulate an IA-32 semaphore if the
IA-32 semaphore is aligned.
• Itanium architecture-based code can only manipulate an IA-32 semaphore if the
IA-32 semaphore is allocated in write-back cacheable memory.
An Itanium architecture-based operating system can emulate IA-32 uncacheable or
misaligned semaphores by using the technique described in the next section.
2.1.3.2 Behavior of Uncacheable and Misaligned Semaphores
A processor based on the Itanium architecture raises an Unsupported Data Reference
fault if it executes a semaphore that accesses a location with a memory attribute that
the semaphore does not support.
If the alignment requirement for Itanium architecture-based semaphores is not met, a
processor based on the Itanium architecture raises an Unaligned Data Reference fault.
This fault is taken regardless of the setting of the user mask alignment checking bit,
UM.ac.
The DCR.lc bit controls how the processor behaves when executing an atomic IA-32
memory reference under an external bus lock. When the DCR.lc bit (see
Section
3.3.4.1, “Default Control Register (DCR – CR0)” ) is 1 and an IA-32 atomic memory
reference requires a non-cacheable or misaligned read-modify-write operation, an
IA_32_Intercept(Lock) fault is raised. Such memory references require an external bus
lock to execute correctly. To preserve
LOCK
pin functionality, an Itanium
architecture-based operating system can virtualize the bus lock by implementing a
shared cacheable global
LOCK
variable.