
2:528
Volume 2, Part 2: MP Coherence and Synchronization
2.4.2
Simple Barrier Synchronization
A barrier is a common synchronization primitive used to hold a set of processes at a
particular point in the program (the barrier) until all processors reach the location.
Once all processes arrive at the barrier, they may all continue to execute.
shows a sense-reversing barrier synchronization based on the
fetchadd
instruction
from Hennessy and Patterson [HP96].
This type of barrier prevents a process that races ahead to the next instance of the
barrier from trapping other (slow) processors that are in the process of leaving the
barrier.
The barrier code begins by atomically updating the number of processors that are
waiting at the barrier,
count
, using a
fetchadd
instruction. For the last processor that
reaches the barrier, the
fetchadd
instruction returns the same value as the
total
shared variable, which is one less than the number of processors that wait at the
barrier. Other processors each get a unique value on the interval [0,
total
) based on
the order in which they arrive at the barrier.
All processors except the last processor wait in the
wait_on_others
loop for the signal
that all have arrived at the barrier. The last processor to arrive at the barrier provides
this signal.
The signal to leave the barrier is deduced from the value of the
release
shared variable
and the
local_sense
local variable. Upon entering the barrier, each processor
complements the value in its private
local_sense
variable. Once in the barrier, all
processors always have the same value in their
local_sense
variables. This variable
Figure 2-5.
Sense-reversing Barrier Synchronization Code
// The total shared variable is one less than the number of processors
// that wait at the barrier.
// The release shared variable indicates if the processor must wait at
// the barrier (initially, this variable is 0).
// local_sense is a per-processor local variable that indicates the
// "sense" of the barrier (initially, this variable is 0).
sr_barrier:
fetchadd8.acq
r1 = [count], 1
// update counter
ld8
r2 = [total]
// get number of procs - 1
ld8
r3 = [local_sense] ;;
// get local “sense” variable
xor
r3 = 1, r3
// local_sense =! local_sense
cmp.eq
p1, p2 = r1, r2;;
// p1 => last proc to arrive
st8
[local_sense] = r3
// save new value of local_sense
(p1)
st8
[count] = r0
// last resets count to 0
(p1)
st8.rel
[release] = r3 ;;
// last allows other to leave
wait_on_others:
(p2)
ld8
r1 = [release] ;;
// p2 => more procs to come
(p2)
cmp.ne.and
p0, p2 = r1, r3
// have all arrived yet?
(p2)
br.cond.sptk
wait_on_others ;;
// nope, continue waiting
// This mf prevents memory operations that follow the barrier code
// from moving ahead of memory operations that precede the barrier
// code
mf ;;
Содержание ITANIUM ARCHITECTURE - SOFTWARE DEVELOPERS VOLUME 3 REV 2.3
Страница 1: ......
Страница 11: ...x Intel Itanium Architecture Software Developer s Manual Rev 2 3 ...
Страница 12: ...1 1 Intel Itanium Architecture Software Developer s Manual Rev 2 3 Part I Application Architecture Guide ...
Страница 13: ...1 2 Intel Itanium Architecture Software Developer s Manual Rev 2 3 ...
Страница 33: ...1 22 Volume 1 Part 1 Introduction to the Intel Itanium Architecture ...
Страница 57: ...1 46 Volume 1 Part 1 Execution Environment ...
Страница 147: ...1 136 Intel Itanium Architecture Software Developer s Manual Rev 2 3 ...
Страница 149: ...1 138 Volume 1 Part 2 About the Optimization Guide ...
Страница 191: ...1 180 Volume 1 Part 2 Predication Control Flow and Instruction Stream ...
Страница 230: ......
Страница 248: ...236 Intel Itanium Architecture Software Developer s Manual Rev 2 3 ...
Страница 249: ...2 1 Intel Itanium Architecture Software Developer s Manual Rev 2 3 Part I System Architecture Guide ...
Страница 250: ...2 2 Intel Itanium Architecture Software Developer s Manual Rev 2 3 ...
Страница 264: ...2 16 Volume 2 Part 1 Intel Itanium System Environment ...
Страница 380: ...2 132 Volume 2 Part 1 Interruptions ...
Страница 398: ...2 150 Volume 2 Part 1 Register Stack Engine ...
Страница 486: ...2 238 Volume 2 Part 1 IA 32 Interruption Vector Descriptions ...
Страница 749: ...2 501 Intel Itanium Architecture Software Developer s Manual Rev 2 3 Part II System Programmer s Guide ...
Страница 750: ...2 502 Intel Itanium Architecture Software Developer s Manual Rev 2 3 ...
Страница 754: ...2 506 Volume 2 Part 2 About the System Programmer s Guide ...
Страница 796: ...2 548 Volume 2 Part 2 Interruptions and Serialization ...
Страница 808: ...2 560 Volume 2 Part 2 Context Management ...
Страница 842: ...2 594 Volume 2 Part 2 Floating point System Software ...
Страница 850: ...2 602 Volume 2 Part 2 IA 32 Application Support ...
Страница 862: ...2 614 Volume 2 Part 2 External Interrupt Architecture ...
Страница 870: ...2 622 Volume 2 Part 2 Performance Monitoring Support ...
Страница 891: ......
Страница 941: ...3 42 Volume 3 Instruction Reference cmp illegal_operation_fault PR p1 0 PR p2 0 Interruptions Illegal Operation fault ...
Страница 1099: ...3 200 Volume 3 Instruction Reference padd Interruptions Illegal Operation fault ...
Страница 1191: ...3 292 Volume 3 Pseudo Code Functions Intel Itanium Architecture Software Developer s Manual Rev 2 3 ...
Страница 1295: ...3 396 Volume 3 Resource and Dependency Semantics ...
Страница 1296: ......
Страница 1302: ...402 Intel Itanium Architecture Software Developer s Manual Rev 2 3 ...
Страница 1494: ...4 192 Volume 4 Base IA 32 Instruction Reference FWAIT Wait See entry for WAIT ...
Страница 1564: ...4 262 Volume 4 Base IA 32 Instruction Reference LES Load Full Pointer See entry for LDS LES LFS LGS LSS ...
Страница 1565: ...Volume 4 Base IA 32 Instruction Reference 4 263 LFS Load Full Pointer See entry for LDS LES LFS LGS LSS ...
Страница 1568: ...4 266 Volume 4 Base IA 32 Instruction Reference LGS Load Full Pointer See entry for LDS LES LFS LGS LSS ...
Страница 1583: ...Volume 4 Base IA 32 Instruction Reference 4 281 LSS Load Full Pointer See entry for LDS LES LFS LGS LSS ...
Страница 1647: ...Volume 4 Base IA 32 Instruction Reference 4 345 ROL ROR Rotate See entry for RCL RCR ROL ROR ...
Страница 1663: ...Volume 4 Base IA 32 Instruction Reference 4 361 SHL SHR Shift Instructions See entry for SAL SAR SHL SHR ...
Страница 1668: ...4 366 Volume 4 Base IA 32 Instruction Reference SIDT Store Interrupt Descriptor Table Register See entry for SGDT SIDT ...
Страница 1884: ...4 582 Volume 4 IA 32 SSE Instruction Reference ...
Страница 1885: ...Index Intel Itanium Architecture Software Developer s Manual Rev 2 3 Index ...
Страница 1886: ...Index Intel Itanium Architecture Software Developer s Manual Rev 2 3 ...
Страница 1898: ...INDEX Index 12 Index for Volumes 1 2 3 and 4 ...