Intel ITANIUM ARCHITECTURE - SOFTWARE DEVELOPERS VOLUME 3 REV 2.3, Руководство пользователя, Страница: 519 / 1898

Volume 2, Part 1: Itanium
®
Architecture-based Operating System Interaction Model with IA-32 Applications 2:271
10.7.2.1 I/O Port Addressing Restrictions
For the 64MB physical I/O port block the following operations are undefined and may
result in unpredictable processor operation; references larger than 4-bytes, instruction
fetch references, references to any memory attribute other than UC, or semaphore
references which require an atomic lock. To ensure I/O ports accesses are not granted
for which the TLB has not been consulted, the processor ensures:
• All byte addresses within the same 4KB page alias to the 4 ports defined by the
mapped physical I/O port page.
• All IA-32 and Itanium unaligned loads and stores that cross a 4-byte boundary to
the processor’s physical I/O port block are truncated. That is the bus transaction to
the area before the 4-byte boundary is performed (the number of bytes emitted is
model specific). No bus transaction is performed for the bytes that are beyond the
4-byte boundary. 4-byte crosser loads while return some undefined data. 4-byte
crosser stores will not write all intended bytes.
• For IA-32 IN/OUT accesses that cross a 4-port boundary the processor will break
the operation into smaller 1, 2, or 3 byte I/O port transactions within each 4KB
virtual page.
10.7.3 IA-32 IN/OUT instructions
IA-32 I/O instructions (IN, OUT, INS, OUTS) defined in the Intel
®
64 and IA-32
Architectures Software Developer’s Manual are augmented as follows:
• I/O instructions first check for IOPL permission. If PSR.cpl<=EFLAG.iopl, access
permission is granted. Otherwise the TSS I/O permission bitmap may be consulted
as defined below. If the Bitmap denies permission or is not consulted an
IA_32_Exception(GPFault) is generated.
• If IOPL permission is denied and CFLG.io is 1, the TSS I/O permission bitmap is
consulted for access permission. If the corresponding bit(s) for the I/O port(s) is 1,
indicating permission is denied, a GPFault is generated. Otherwise access
permission is granted. The TSS I/O permission bitmap provides 1 port permission
control at the expense of additional processor data memory references. This
mechanism can be used in the Itanium System Environment, but is not
recommended since TLB access controls defined by the Itanium architecture are
faster and provide a consistent control mechanism for both IA-32 and Itanium
architecture-based code. Whereas, the TLB mechanism provides a control
mechanism for both IA-32 and Itanium memory references.
• If CFLG.io is 0, the TSS I/O permission bitmap is not consulted and if the IOPL
check failed an IA_32_Exception(GPFault) is generated. By setting CFLG.io to 0,
operating system code can disable all processor references to the TSS. By setting
IOPL<PSR.cpl and setting CFLG.io to 0, operating system code can block all user
level execution of IA-32 I/O instructions, no TSS needs to be allocated or defined by
the operating system.
• I/O port references generate a virtual port address relative to the IOBase register
as defined in Section 10.7.1, “Virtual I/O Port Addressing” on page 2:268 .
• If data translations are enabled, the TLB is consulted for the required virtual to
physical mapping. If the required mapping is not present a VHPT Translation, Data
TLB Miss or Alternative Data TLB Miss fault is generated.
• If data translations are enabled, Access Rights, Permission Keys, Access, Dirty and
Present bits are checked and faults generated.