1:160
Volume 1, Part 2: Memory Reference
A disadvantage of post-increment loads is that they create new dependencies between
post-increment loads and the operations that use the post-increment values. In some
cases, the compiler may wish to separate post-increment loads into their component
instructions to improve the overall schedule. Alternatively, the compiler could wait until
after instruction scheduling and then opportunistically find places where post-increment
loads could be substituted for separate load and add instructions.
3.5.5
Loop Optimization
In cyclic code, speculation can extend the use of classical loop optimizations like
invariant code motion. Examine this pseudo-code:
while (cond) {
c = a + b; // Probably loop invariant
*ptr++ = c;// May point to a or b
}
The variables
a
and
b
are probably loop invariant; however, the compiler must assume
the stores to
*ptr
will overwrite the values of
a
and
b
unless analysis can guarantee
that this can never happen. The use of advanced loads and checks allows code that is
likely to be invariant to be removed from a loop, even when a pointer cannot be
disambiguated:
ld4.a
r1 = [&a]
ld4.a
r2 = [&b]
add
r3 = r1,r2 // Move computation out of loop
while (cond) {
chk.a.nc r1, recover1
L1:
chk.a.nc r2, recover2
L2:
*p++ = r3
}
At the end of the module:
recover1:
// Recover from failed load of a
ld4.a
r1 = [&a]
add
r3 = r1, r2
br.sptk L1
// Unconditional branch
recover2:
// Recover from failed load of b
ld4.a
r2 = [&b]
add
r3 = r1, r2
br.sptk L2
// Unconditional branch
Using speculation in this loop hides the latency of the calculation of
c
whenever the
speculated code is successful.
Since checks have both a clear (clr) and no clear (nc) form, the programmer must
decide which to use. This example shows that when checks are moved out of loops, the
no clear version should be used. This is because the clear (clr) version will cause the
corresponding ALAT entry to be removed (which would cause the next check to that
register to fail).
Содержание ITANIUM ARCHITECTURE - SOFTWARE DEVELOPERS VOLUME 3 REV 2.3
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Страница 11: ...x Intel Itanium Architecture Software Developer s Manual Rev 2 3 ...
Страница 12: ...1 1 Intel Itanium Architecture Software Developer s Manual Rev 2 3 Part I Application Architecture Guide ...
Страница 13: ...1 2 Intel Itanium Architecture Software Developer s Manual Rev 2 3 ...
Страница 33: ...1 22 Volume 1 Part 1 Introduction to the Intel Itanium Architecture ...
Страница 57: ...1 46 Volume 1 Part 1 Execution Environment ...
Страница 147: ...1 136 Intel Itanium Architecture Software Developer s Manual Rev 2 3 ...
Страница 149: ...1 138 Volume 1 Part 2 About the Optimization Guide ...
Страница 191: ...1 180 Volume 1 Part 2 Predication Control Flow and Instruction Stream ...
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Страница 249: ...2 1 Intel Itanium Architecture Software Developer s Manual Rev 2 3 Part I System Architecture Guide ...
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Страница 264: ...2 16 Volume 2 Part 1 Intel Itanium System Environment ...
Страница 380: ...2 132 Volume 2 Part 1 Interruptions ...
Страница 398: ...2 150 Volume 2 Part 1 Register Stack Engine ...
Страница 486: ...2 238 Volume 2 Part 1 IA 32 Interruption Vector Descriptions ...
Страница 749: ...2 501 Intel Itanium Architecture Software Developer s Manual Rev 2 3 Part II System Programmer s Guide ...
Страница 750: ...2 502 Intel Itanium Architecture Software Developer s Manual Rev 2 3 ...
Страница 754: ...2 506 Volume 2 Part 2 About the System Programmer s Guide ...
Страница 796: ...2 548 Volume 2 Part 2 Interruptions and Serialization ...
Страница 808: ...2 560 Volume 2 Part 2 Context Management ...
Страница 842: ...2 594 Volume 2 Part 2 Floating point System Software ...
Страница 850: ...2 602 Volume 2 Part 2 IA 32 Application Support ...
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Страница 1099: ...3 200 Volume 3 Instruction Reference padd Interruptions Illegal Operation fault ...
Страница 1191: ...3 292 Volume 3 Pseudo Code Functions Intel Itanium Architecture Software Developer s Manual Rev 2 3 ...
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Страница 1494: ...4 192 Volume 4 Base IA 32 Instruction Reference FWAIT Wait See entry for WAIT ...
Страница 1564: ...4 262 Volume 4 Base IA 32 Instruction Reference LES Load Full Pointer See entry for LDS LES LFS LGS LSS ...
Страница 1565: ...Volume 4 Base IA 32 Instruction Reference 4 263 LFS Load Full Pointer See entry for LDS LES LFS LGS LSS ...
Страница 1568: ...4 266 Volume 4 Base IA 32 Instruction Reference LGS Load Full Pointer See entry for LDS LES LFS LGS LSS ...
Страница 1583: ...Volume 4 Base IA 32 Instruction Reference 4 281 LSS Load Full Pointer See entry for LDS LES LFS LGS LSS ...
Страница 1647: ...Volume 4 Base IA 32 Instruction Reference 4 345 ROL ROR Rotate See entry for RCL RCR ROL ROR ...
Страница 1663: ...Volume 4 Base IA 32 Instruction Reference 4 361 SHL SHR Shift Instructions See entry for SAL SAR SHL SHR ...
Страница 1668: ...4 366 Volume 4 Base IA 32 Instruction Reference SIDT Store Interrupt Descriptor Table Register See entry for SGDT SIDT ...
Страница 1884: ...4 582 Volume 4 IA 32 SSE Instruction Reference ...
Страница 1885: ...Index Intel Itanium Architecture Software Developer s Manual Rev 2 3 Index ...
Страница 1886: ...Index Intel Itanium Architecture Software Developer s Manual Rev 2 3 ...
Страница 1898: ...INDEX Index 12 Index for Volumes 1 2 3 and 4 ...