1:110
Volume 1, Part 1: IA-32 Application Execution Model in an Intel
®
Itanium
®
System Environment
The Itanium architecture can support 16-bit Real Mode, 16-bit VM86, and 16-bit/32-bit
Protected Mode IA-32 applications in the context of an Itanium architecture-based
operating system. Whether an IA-32 application is actually supported on specific
operating systems is determined by the infrastructure provided by that specific
operating system.
6.2.1
Instruction Set Modes
The processor can be executing either IA-32 or Itanium instructions at any point in
time. PSR.is (defined in
Section 3.3.2, “Processor Status Register (PSR)” on page 2:23
)
specifies the currently executing instruction set, where 1 indicates IA-32 instructions
are executing, and 0 indicates Itanium instructions are executing. Three special
instructions and interruptions are defined to transition the processor between the IA-32
and the Itanium instruction sets as shown in
.
•
jmpe
(IA-32 instruction) Jump to an Itanium target instruction, and transition to the
Itanium instruction set.
•
br.ia
(Itanium instruction) Branch to an IA-32 target instruction, and change the
instruction set to IA-32.
•
rfi
(Itanium instruction) “Return from interruption” is defined to return to either an
IA-32 or Itanium instruction when resuming from an interruption.
• Interruptions
transition the processor to the Itanium instruction set for all
interruption conditions.
The
jmpe
and
br.ia
instructions provide a low overhead mechanism to transfer control
between the instruction sets. These primitives typically are incorporated into “thunks”
or “stubs” that implement the required call linkage and calling conventions to call
dynamic or statically linked libraries.
6.2.1.1
Instruction Set Execution in the Intel
®
Itanium
®
Architecture
While the processor executes from the Itanium instruction set (PSR.is is 0):
• Itanium instructions are fetched, decoded and executed by the processor.
• Itanium instructions can access the entire Itanium and IA-32 application register
state. This includes IA-32 segment descriptors, selectors, general registers,
physical floating-point registers, MMX technology registers, and SSE registers. See
Figure 6-1.
Instruction Set Transition Model
IA-32 Instruction
jmpe
br.ia
Intercepts,
Exceptions,
Software Interrupts
rfi
Interruptions
Set
Intel
®
Itanium
®
Instruction Set
Intel
®
Itanium
®
System Environment
Содержание ITANIUM ARCHITECTURE - SOFTWARE DEVELOPERS VOLUME 3 REV 2.3
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Страница 11: ...x Intel Itanium Architecture Software Developer s Manual Rev 2 3 ...
Страница 12: ...1 1 Intel Itanium Architecture Software Developer s Manual Rev 2 3 Part I Application Architecture Guide ...
Страница 13: ...1 2 Intel Itanium Architecture Software Developer s Manual Rev 2 3 ...
Страница 33: ...1 22 Volume 1 Part 1 Introduction to the Intel Itanium Architecture ...
Страница 57: ...1 46 Volume 1 Part 1 Execution Environment ...
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Страница 149: ...1 138 Volume 1 Part 2 About the Optimization Guide ...
Страница 191: ...1 180 Volume 1 Part 2 Predication Control Flow and Instruction Stream ...
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Страница 249: ...2 1 Intel Itanium Architecture Software Developer s Manual Rev 2 3 Part I System Architecture Guide ...
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Страница 264: ...2 16 Volume 2 Part 1 Intel Itanium System Environment ...
Страница 380: ...2 132 Volume 2 Part 1 Interruptions ...
Страница 398: ...2 150 Volume 2 Part 1 Register Stack Engine ...
Страница 486: ...2 238 Volume 2 Part 1 IA 32 Interruption Vector Descriptions ...
Страница 749: ...2 501 Intel Itanium Architecture Software Developer s Manual Rev 2 3 Part II System Programmer s Guide ...
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Страница 754: ...2 506 Volume 2 Part 2 About the System Programmer s Guide ...
Страница 796: ...2 548 Volume 2 Part 2 Interruptions and Serialization ...
Страница 808: ...2 560 Volume 2 Part 2 Context Management ...
Страница 842: ...2 594 Volume 2 Part 2 Floating point System Software ...
Страница 850: ...2 602 Volume 2 Part 2 IA 32 Application Support ...
Страница 862: ...2 614 Volume 2 Part 2 External Interrupt Architecture ...
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Страница 941: ...3 42 Volume 3 Instruction Reference cmp illegal_operation_fault PR p1 0 PR p2 0 Interruptions Illegal Operation fault ...
Страница 1099: ...3 200 Volume 3 Instruction Reference padd Interruptions Illegal Operation fault ...
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Страница 1494: ...4 192 Volume 4 Base IA 32 Instruction Reference FWAIT Wait See entry for WAIT ...
Страница 1564: ...4 262 Volume 4 Base IA 32 Instruction Reference LES Load Full Pointer See entry for LDS LES LFS LGS LSS ...
Страница 1565: ...Volume 4 Base IA 32 Instruction Reference 4 263 LFS Load Full Pointer See entry for LDS LES LFS LGS LSS ...
Страница 1568: ...4 266 Volume 4 Base IA 32 Instruction Reference LGS Load Full Pointer See entry for LDS LES LFS LGS LSS ...
Страница 1583: ...Volume 4 Base IA 32 Instruction Reference 4 281 LSS Load Full Pointer See entry for LDS LES LFS LGS LSS ...
Страница 1647: ...Volume 4 Base IA 32 Instruction Reference 4 345 ROL ROR Rotate See entry for RCL RCR ROL ROR ...
Страница 1663: ...Volume 4 Base IA 32 Instruction Reference 4 361 SHL SHR Shift Instructions See entry for SAL SAR SHL SHR ...
Страница 1668: ...4 366 Volume 4 Base IA 32 Instruction Reference SIDT Store Interrupt Descriptor Table Register See entry for SGDT SIDT ...
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Страница 1885: ...Index Intel Itanium Architecture Software Developer s Manual Rev 2 3 Index ...
Страница 1886: ...Index Intel Itanium Architecture Software Developer s Manual Rev 2 3 ...
Страница 1898: ...INDEX Index 12 Index for Volumes 1 2 3 and 4 ...