Intel ITANIUM ARCHITECTURE - SOFTWARE DEVELOPERS VOLUME 3 REV 2.3, Руководство пользователя

Страница: 202 / 1898

Volume 1, Part 2: Software Pipelining and Loop Support 1:191
Notice that the load for the second source iteration is executed before the compare and
branch of the first source iteration. That is, the load (and the update of
r5
) is
speculative. The loop condition is not computed until cycle X+2, but in order to
maximize the use of resources, it is desirable to start the second source iteration at
cycle X+1. Without the support for control speculation in the Itanium architecture, the
second source iteration could not be started until cycle X+3.
The computation of the loop condition for while loops is very different from that of
counted loops. In counted loops, it is possible to compute the loop condition in one
cycle using a counted loop branch. This is what a
br.ctop
instruction does when it sets
p16
. In while loops, a compare must compute the loop condition and set the stage
predicates. The stages prior to the one containing the compare are called the
speculative stages of the pipeline, because it is not possible for the compare to
completely control the execution of these stages. Therefore, the stage predicate set by
the compare is used (after rotation) to control the first non-speculative stage of the
pipeline.
The pipelined version of the while loop on page 1:190 is shown below. A check for the
speculative load is included:
mov ec = 2
mov pr.rot = 1 << 16;; // PR16 = 1, rest = 0
L1:
ld4.s r32 = [r5],4 // Cycle 0
(p18) chk.s r34, recovery // Cycle 0
(p18) cmp.ne p17,p0 = r34,r0 // Cycle 0
(p18) st4 [r6] = r34,4 // Cycle 0
(p17) br.wtop.sptkL1;; // Cycle 0
L2:
To explain why the kernel loop is programmed the way it is, it is helpful to examine a
trace of the execution of the loop (assume there are 200 source iterations) shown in
Table 5-2 .
There is no stage predicate assigned to the load because it is speculative. The compare
sets
p17
. This is the branch predicate for the current iteration and, after rotation, the
stage predicate for the first non-speculative stage (stage three) of the next source
iteration. During the prolog, the compare cannot produce its first valid result until cycle
two. The initialization of the predicates provides a pipeline that disables the compare
until the first source iteration reaches stage two in cycle two. At that point the
compare starts generating stage predicates to control the non-speculative stages of the
pipeline. Notice that the compare is conditional. If it were unconditional, it would
always write a zero to
p17
and the pipeline would not get started correctly.
Table 5-2. wtop Loop Trace
Cycle
Port/Instructions State before br.wtop
M I I M B p16 p17 p18 EC
0 ld4.s br.wtop 1 0 0 2
1 ld4.s br.wtop 0 1 0 1
2 ld4.s cmp chk st4 br.wtop 0 1 1 1