Intel ITANIUM ARCHITECTURE - SOFTWARE DEVELOPERS VOLUME 3 REV 2.3, Руководство пользователя, Страница: 813 / 1898

Volume 2, Part 2: Memory Management 2:565
running, the OS will insert a valid PKR with the protection key 0xA and the ‘rd’ bit
cleared, to allow this process to read from the page. However, the ‘wd’ bit for this PKR
will be set when the consumer process is running to prevent it from writing the page.
The processor hardware has no notion of which protection keys belong to which
process. The only check the hardware performs is to compare the protection key from
the translation to any valid protection keys in the PKR cache. On a context switch, the
OS must purge any valid protection keys from the PKRs which would provide access
rights to the switched-to context that are not allowed. The OS may purge an existing
PKR by performing a move to PKR instruction with the same key as the existing PKR,
but with the PKR valid bit set to 0.
Protection keys can be read from the processor’s data TLBs via the
tak
instruction.
However, instruction TLB key values cannot be read directly. Software must keep track
of these values in its own data structures.
5.1.2.1 Single Address Space Operating Systems
Processes in a single address space (SAS) OS all cohabit a global address space. SAS
operating systems running on a processor based on the Itanium architecture can view
the RID bits as effectively extending the single virtual address space to between 79 and
85 bits (depending on the number of RID bits implemented by the processor). This
address space is then divided into between 2
18
and 2
24
61-bit regions, up to eight of
which may be accessed concurrently.
Note that there is no “SAS OS” or “MAS OS” mode in the Itanium architecture. The
processor behavior is the same, regardless of the address space model used by the OS.
The difference between a SAS OS and a MAS OS is one of OS policy: specifically how
the RIDs and protection keys are managed by the OS, and whether different processes
are permitted to share RIDs for their private code and data. Multiple, unrelated
processes in a SAS OS may share the same RID for their private pages; it is the
responsibility of the OS to use protection keys and the protection key registers (PKRs)
to enforce protection. In a MAS OS, the unique per-process RIDs enforce this
protection.
Hybrid SAS/MAS models that combine unique RIDs for process-private regions and
shared RIDs with protection keys for per-page memory protection in shared regions are
also possible.
5.2 Translation Lookaside Buffers (TLBs)
All processors based on the Itanium architecture implement one or more translation
lookaside buffers (TLBs) for fast virtual-to-physical address translation. The
architecture provides instructions for managing instruction and data TLBs as separate
structures.
Both the instruction and data TLBs are further divided into a set of translation registers
(TRs), which are managed exclusively by software and are “locked down” to pin critical
address translations (e.g. kernel memory); and a set of translation cache entries (TCs),
which can be managed by both software and the processor hardware. The TRs are
divided into slots, each of which are individually addressable on insertion by software.