Intel ITANIUM ARCHITECTURE - SOFTWARE DEVELOPERS VOLUME 3 REV 2.3, Руководство пользователя, Страница: 795 / 1898

Volume 2, Part 2: Interruptions and Serialization 2:547
heavyweight interruption handler), we say that a nested interruption has occurred. On
a nested interruption (other than a Data Nested TLB fault) only ISR is updated by the
hardware. All other interruption registers preserve their pre-interruption contents.
With the exception of the Data Nested TLB fault, the Itanium architecture does not
support nested interruptions. Data Nested TLB faults are special and are discussed in
Section 5.4.4, “Data Nested TLB Vector” on page 2:576 . The remainder of this section
does not apply to Data Nested TLB faults.
When a nested interruption occurs, the processor will update ISR as defined in
Chapter 8, “Interruption Vector Descriptions” and it will set the ISR.ni bit to 1. A value
of 1 in ISR.ni is the only indication to an interruption handler that a nested interruption
has occurred. Since all other interruption registers are not updated, there is generally
no way for the OS to recover from nested interruptions; the handler for the nested
interruption has no context other than ISR for handling the nested interruption. If a
nested interruption is detected, it is often useful for the handler to call some function in
the OS that logs the state of ISR, IIP, and any other relevant register state to aid in
debugging the problem.
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