Intel ITANIUM ARCHITECTURE - SOFTWARE DEVELOPERS VOLUME 3 REV 2.3, Руководство пользователя

Страница: 1222 / 1898

Volume 3: Instruction Formats 3:323
4.3.9 Test Feature
I30
4.4 M-Unit Instruction Encodings
4.4.1 Loads and Stores
All load and store instructions are encoded within major opcodes 4, 5, 6, and 7 using a
6-bit opcode extension field in bits 35:30 (x
6
). Instructions in major opcode 4 (integer
load/store, semaphores, and get FR) use two 1-bit opcode extension fields in bit 36 (m)
and bit 27 (x) as shown in
Table 4-28 . Instructions in major opcode 6 (floating-point
load/store, load pair, and set FR) use two 1-bit opcode extension fields in bit 36 (m)
and bit 27 (x) as shown in
Table 4-29 .
The integer load/store opcode extensions are summarized in Table 4-30 on page 3:324 ,
Table 4-31 on page 3:324 , and Table 4-32 on page 3:325 , and the semaphore and get
FR opcode extensions in Table 4-33 on page 3:325 . The floating-point load/store
40 37 36 35 34 33 32 27 26 20 19 18 14 13 12 11 6 5 0
5 t
b
x
2
t
a
p
2
0 x imm
5b
y c p
1
qp
4 1 2 1 6 7 1 5 1 1 6 6
Instruction Operands Opcode
Extension
x
2
t
a
t
b
y x c
tf.z
p
1
, p
2
= imm
5
5 0
0
0
1 1
0
tf.z.unc 1
tf.z.and
1
0
tf.nz.and 1
tf.z.or
1
0
0
tf.nz.or 1
tf.z.or.andcm
1
0
tf.nz.or.andcm 1
Table 4-28. Integer Load/Store/Semaphore/Get FR 1-bit Opcode
Extensions
Opcode
Bits 40:37
m
Bit 36
x
Bit 27
4
0 0 Load/Store ( Table 4-30 )
0 1 Semaphore/get FR ( Table 4-33 )
1 0 Load +Reg ( Table 4-31 )
1 1
Table 4-29. Floating-point Load/Store/Load Pair/Set FR 1-bit Opcode
Extensions
Opcode
Bits 40:37
m
Bit 36
x
Bit 27
6
0 0 FP Load/Store ( Table 4-34 )
0 1 FP Load Pair/set FR ( Table 4-37 )
1 0 FP Load +Reg ( Table 4-35 )
1 1 FP Load Pair +Imm ( Table 4-38 )