Intel ITANIUM ARCHITECTURE - SOFTWARE DEVELOPERS VOLUME 3 REV 2.3, Руководство пользователя, Страница: 195 / 1898

1:184 Volume 1, Part 2: Software Pipelining and Loop Support
the loop has the same schedule. It is likely that software pipelining algorithms other
than modulo scheduling could benefit from the loop support features. Therefore the
examples in this chapter are discussed in terms of software pipelining rather than
modulo scheduling.
Software pipelined loops have three phases: prolog, kernel, and epilog, as shown
below:
1 2 3 4 5 Phase
----------------------------------------------------
ld4
ld4
Prolog
add ld4
----------------------------------------------------
st4 add
ld4 Kernel
st4 add ld4
------------------------------------------------------
st4 add
st4 add Epilog
st4
During the prolog phase, a new loop iteration is started every II cycles (every cycle for
the above example) to fill the pipeline. During the first cycle of the prolog, stage 1 of
the first iteration executes. During the second cycle, stage 1 of the second iteration and
stage 2 of the first iteration execute, etc. By the start of the kernel phase, the pipeline
is full. Stage 1 of the fourth iteration, stage 2 of the third iteration, stage 3 of the
second iteration, and stage 4 of the first iteration execute. During the kernel phase, a
new loop iteration is started, and another is completed every II cycles. During the
epilog phase, no new iterations are started, but the iterations already in progress are
completed, draining the pipeline. In the above example, iterations 3-5 are completed
during the epilog phase.
The software pipeline is coded as a loop that is very different from the original source
code loop. To avoid confusion when discussing loops and loop iterations, we use the
term
source loop and source iteration to refer back to the original source code loop, and
the term kernel loop and kernel iteration to refer to the loop that implements the
software pipeline.
In the above example, the load from the second source iteration is issued before result
of the first load is consumed. Thus, in many cases, loads from successive iterations of
the loop must target different registers to avoid overwriting existing live values. In
traditional architectures, this requires unrolling of the kernel loop and software
renaming of the registers, resulting in code expansion. Furthermore, in traditional
architectures, separate blocks of code are generated for the prolog, kernel, and epilog
phases, resulting in additional code expansion.
5.4 Loop Support Features in the Intel
®
Itanium
®
Architecture
The code expansion that results from loop optimizations (such as software pipelining
and loop unrolling) on traditional architectures can increase the number of instruction
cache misses, thus reducing overall performance. The loop support features in the