Intel ITANIUM ARCHITECTURE - SOFTWARE DEVELOPERS VOLUME 3 REV 2.3, Руководство пользователя

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2:112 Volume 2, Part 1: Interruptions
greater than the page boundary, any Instruction TLB faults on the second page
have higher priority than the IA-32 Code Fetch fault.
Class B
–
Faults from decoding an instruction. Priority of IA-32 Instruction Length,
IA-32 Invalid Opcode, and IA-32 Instruction Intercept, Disabled Floating Point Register,
Disabled Instruction Set Transition, and Device Not Available faults are model specific.
If the IA-32 instruction spans a virtual page, IA-32 Instruction Length >15 byte Faults
(IA_32_Exception(GPFault)) can have higher priority than Instruction TLB faults as
defined below:
• If the IA-32 prefix bytes on the first page are >= 15 bytes, an IA-32 Instruction
>15 byte fault (GPFault) is taken first regardless of any Instruction TLB faults on
the second page.
• If the IA-32 prefix bytes on the first page are < 15 bytes, Instruction TLB faults on
the second page may or may not have priority over any possible IA-32 Instruction
Length fault.
Class C
–
Faults resulting from executing an instruction. Priority of faults is model
specific and can vary across processor implementations. Most faults are related to data
memory references, other fault priorities can vary due to model-specific differences
across processor implementations. The memory fault priorities (IA-32 Stack Exception
through Data Access Bit fault) defined in the table only apply to a single IA-32 data
memory reference that does not cross a virtual page. If an IA-32 instruction requires
multiple data memory references or a single data memory reference crosses a virtual
page:
• If any given IA-32 instruction requires multiple data memory references, all
possible faults are raised on the first data memory reference before any faults are
checked on subsequent data memory references. This implies lower priority faults
on an earlier memory reference will be raised before higher priority faults on a later
data memory reference within a single IA-32 instruction. The order of data memory
references initiated by an IA-32 instruction is implementation dependent and may
vary from processor to processor. Software can not assume all higher priority data
memory faults are raised before all lower priority data memory faults within a
single IA-32 instruction.
• If a single IA-32 data memory reference crosses a virtual page, the processor
checks for faults in a model-specific order: Any faults present on one page are
checked and reported before any faults are checked and reported on the other
page. This implies that a single data reference that crosses a virtual page can raise
lower priority data memory faults on one page before higher priority data memory
faults are raised on the other page. For example, Data Key Miss faults (lower
priority) on the first page could be raised before a Data TLB Miss Fault (higher
priority) on the second page. Software can not assume all higher priority data
memory faults are raised before all lower priority data memory faults within a
single IA-32 instruction.
Class D
–
Traps on the current IA-32 instruction. Trap conditions are reported
concurrently on the same exception vector or via a trap code specifying all concurrent
traps.