Intel ITANIUM ARCHITECTURE - SOFTWARE DEVELOPERS VOLUME 3 REV 2.3, Руководство пользователя, Страница: 274 / 1898

2:26 Volume 2, Part 1: System State and Programming Model
dfh 19 Disabled Floating-point High register set – When 1, a
read or write access to f32 through f127 results in a
Disabled Floating-Point Register fault. When 1, a
Disabled FP Register fault is raised on the first IA-32
target instruction following a
br.ia or rfi , regardless
whether f32-127 are referenced.
0 data
sp 20 Secure Performance monitors – Controls the ability of
non-privileged code (including IA-32 code) to read
non-privileged performance monitors. See
Table 7-5 on
page 2:158 for values returned by PMD read
instructions. Also, when 0, PSR.up can be modified by
user mask instructions; otherwise, PSR.up is
unchanged by user mask instructions. When 1 or
CFLG.pce is 0, non-privileged IA-32 performance
monitor reads (via
rdpmc
) raise an
IA_32_Exception(GPFault).
0 data
pp 21 Privileged Performance monitor enable – When 1,
monitors configured as privileged monitors are enabled
to count events (including IA-32 events). When 0,
privileged monitors are disabled. See
“Performance
Monitoring” on page 2:155 for details.
DCR.pp inst/data
e
di 22 Disable Instruction set transition – When 1, attempts to
switch instruction sets via the IA-32
jmpe
or
br.ia
instructions results in a Disabled Instruction Set
Transition fault. This bit doesn’t restrict instruction set
transitions due to interruptions or
rfi
.
0 data
si 23 Secure Interval timer – When 1, the Interval Time
Counter (ITC) register and the Resource Utilization
Counter (RUC) are readable only by privileged code;
non-privileged reads result in a Privileged Register
fault. When 0, ITC and RUC are readable at any
privilege level. System software can secure the ITC
from non-privileged IA-32 access by setting either
PSR.si or CFLG.tsd to 1. When secured, an IA-32 rdtsc
(read time stamp counter) instruction at any privilege
level other than the most privileged raises an
IA_32_Exception(GPfault) 0 data
PSR.l = PSR{31:0}
db
24 Debug Breakpoint fault – When 1, data and instruction
address breakpoints are enabled and can cause an
Data/Instruction Debug fault. When 1, IA-32 instruction
address breakpoints are enabled and can cause an
IA_32_Exception(Debug) fault.When 1, IA-32 data
address breakpoints are enabled and can cause an
IA_32_Exception(Debug) Trap.When 0, address
breakpoint faults and traps are disabled. 0 inst/data
e
lp 25 Lower Privilege transfer trap – When 1, a Lower
Privilege Transfer trap occurs whenever a taken branch
lowers the current privilege level (numerically
increases). This bit is ignored during IA-32 instruction
set execution. 0 data
Table 3-2. Processor Status Register Fields (Continued)
Field Bits Description
Interruption
State
Serialization
Required