Atmel ATSAML22G16A-AUT, Руководство пользователя

Страница: 249 / 1231

21.8.11. DFLL48M Multiplier
Name: DFLLMUL
Offset: 0x20
Reset: 0x00000000
Property:
PAC Write-Protection, Write-Synchronized using STATUS.DFLLRDY=1
Bit 31 30 29 28 27 26 25 24
CSTEP[5:0] FSTEP[9:8]
Access R R R R R R R/W R/W
Reset 0 0 0 0 0 0 0 0
Bit 23 22 21 20 19 18 17 16
FSTEP[7:0]
Access R/W R/W R/W R/W R/W R/W R/W R/W
Reset 0 0 0 0 0 0 0 0
Bit 15 14 13 12 11 10 9 8
MUL[15:8]
Access R/W R/W R/W R/W R/W R/W R/W R/W
Reset 0 0 0 0 0 0 0 0
Bit 7 6 5 4 3 2 1 0
MUL[7:0]
Access R/W R/W R/W R/W R/W R/W R/W R/W
Reset 0 0 0 0 0 0 0 0
Bits 31:26 – CSTEP[5:0]: Coarse Maximum Step
This bit group indicates the maximum step size allowed during coarse adjustment in closed-loop mode.
When adjusting to a new frequency, the expected output frequency overshoot depends on this step size.
Bits 25:16 – FSTEP[9:0]: Fine Maximum Step
This bit group indicates the maximum step size allowed during fine adjustment in closed-loop mode.
When adjusting to a new frequency, the expected output frequency overshoot depends on this step size.
Bits 15:0 – MUL[15:0]: DFLL Multiply Factor
This field determines the ratio of the CLK_DFLL output frequency to the CLK_DFLL_REF input frequency.
Writing to the MUL bits will cause locks to be lost and the fine calibration value to be reset to its midpoint.
Atmel SAM L22G / L22J / L22N [DATASHEET]
Atmel-42402E-SAM L22G / L22J / L22N_Datasheet_Complete-07/2016
249