254
MicroBlaze Processor Reference Guide
UG081 (v14.7)
Chapter 5:
MicroBlaze Instruction Set Architecture
swx
Store Word Exclusive
Description
Conditionally stores the contents of register rD, into the word aligned memory location that results
from adding the contents of registers rA and rB. If an AXI4 interconnect with exclusive access
enabled is used, the store occurs if the interconnect response is EXOKAY, and the reservation bit is
set; otherwise the store occurs when the reservation bit is set. The carry flag (MSR[C]) is set if the
store does not occur, otherwise it is cleared. The reservation bit is cleared.
A data TLB miss exception occurs if virtual protected mode is enabled, and a valid translation entry
corresponding to the address is not found in the TLB.
A data storage exception occurs if virtual protected mode is enabled, and access is prevented by no-
access-allowed or read-only zone protection. No-access-allowed can only occur in user mode.
An unaligned data access exception will
not
occur even if the two least significant bits in the address
are not zero.
Enabling AXI exclusive access ensures that the operation is protected from other bus masters, but
requires that the addressed slave supports exclusive access. When exclusive access is not enabled,
only the internal reservation bit is used. Exclusive access is enabled using the two parameters
C_M_AXI_DP_EXCLUSIVE_ACCESS
and
C_M_AXI_DC_EXCLUSIVE_ACCESS
for the
peripheral and cache interconnect, respectively.
Pseudocode
Addr
←
(rA) + (rB)
if Reservation = 0 then
MSR[C]
←
1
else
if TLB_Miss(Addr) and MSR[VM] = 1 then
ESR[EC]
←
10010;ESR[S]
←
1
MSR[UMS]
←
MSR[UM]; MSR[VMS]
←
MSR[VM]; MSR[UM]
←
0; MSR[VM]
←
0
else if Access_Protected(Addr) and MSR[VM] = 1 then
ESR[EC]
←
10000;ESR[S]
←
1; ESR[DIZ]
←
No-access-allowed
MSR[UMS]
←
MSR[UM]; MSR[VMS]
←
MSR[VM]; MSR[UM]
←
0; MSR[VM]
←
0
else
Reservation
← 0
if AXI_Exclusive(Addr) and AXI_Response
≠
EXOKAY then
MSR[C]
← 1
else
Mem(Addr)
← (
rD)[0:31]
MSR[C]
← 0
swx
rD, rA, rB
1 1 0 1 1 0
rD
rA
rB
1 0 0 0 0 0 0 0 0 0 0
0
6
11
16
21
31
