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MicroBlaze Processor Reference Guide

245

UG081 (v14.7)

Instructions

sh

Store Halfword

Description

Stores the contents of the least significant halfword of register rD, into the halfword aligned memory
location that results from adding the contents of registers rA and rB.

If the R bit is set, a halfword reversed memory location is used and the two bytes in the halfword are
reversed, storing data with the opposite endianness of the endianness defined by

C_ENDIANNESS

and the E bit (if virtual protected mode is enabled).

A data TLB miss exception occurs if virtual protected mode is enabled, and a valid translation entry
corresponding to the address is not found in the TLB.

A data storage exception occurs if virtual protected mode is enabled, and access is prevented by no-
access-allowed or read-only zone protection. No-access-allowed can only occur in user mode.

An unaligned data access exception occurs if the least significant bit in the address is not zero.

Pseudocode

Addr

←

(rA) + (rB)

if TLB_Miss(Addr) and MSR[VM] = 1 then

ESR[EC]

←

10010;ESR[S]

←

1

MSR[UMS]

←

MSR[UM]; MSR[VMS]

←

MSR[VM]; MSR[UM]

←

0; MSR[VM]

←

0

else if Access_Protected(Addr) and MSR[VM] = 1 then

ESR[EC]

←

10000;ESR[S]

←

1; ESR[DIZ]

←

No-access-allowed

MSR[UMS]

←

MSR[UM]; MSR[VMS]

←

MSR[VM]; MSR[UM]

←

0; MSR[VM]

←

0

else if Addr[31]

≠

0 then

ESR[EC]

←

00001; ESR[W]

←

0; ESR[S]

←

1; ESR[Rx]

←

rD

else

Mem(Addr)

←

(rD)[16:31]

Registers Altered

•

MSR[UM], MSR[VM], MSR[UMS], MSR[VMS], if a TLB miss exception or a data storage
exception is generated

•

ESR[EC], ESR[S], if an exception is generated

•

ESR[DIZ], if a data storage exception is generated

•

ESR[W], ESR[Rx], if an unaligned data access exception is generated

Latency

•

1 cycle with

C_AREA_OPTIMIZED=0

•

2 cycles with

C_AREA_OPTIMIZED=1

Note

The halfword reversed instruction is only valid if MicroBlaze is configured to use reorder
instructions (

C_USE_REORDER_INSTR = 1

).

sh

rD, rA, rB

shr

rD, rA, rB

1 1 0 1 0 1

rD

rA

rB

0 R 0 0 0 0 0 0 0 0 0

0

6

11

16

21

31

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Summary of Contents for MicroBlaze

Page 1: ...MicroBlaze Processor Reference Guide Embedded Development Kit EDK 14 7 UG081 v14 7...

Page 2: ...d to be fail safe or for use in any application requiring fail safe performance you assume sole risk and liability for use of Xilinx products in Critical Applications http www xilinx com warranty htm...

Page 3: ...corrections for EDK 10 1 SP3 release 02 04 09 10 0 Xilinx EDK 11 1 release 04 15 09 10 1 Xilinx EDK 11 2 release 05 28 09 10 2 Xilinx EDK 11 3 release 10 26 09 10 3 Xilinx EDK 11 4 release 04 19 10 11...

Page 4: ...MicroBlaze Processor Reference Guide www xilinx com UG081 v14 7...

Page 5: ...PU 80 Stream Link Interfaces 84 Debug and Trace 85 Fault Tolerance 86 Lockstep Operation 92 Chapter 3 MicroBlaze Signal Interface Description Overview 95 MicroBlaze I O Overview 96 AXI4 and ACE Interf...

Page 6: ...ter Usage Conventions 152 Stack Convention 153 Memory Model 155 Interrupt and Exception Handling 156 Chapter 5 MicroBlaze Instruction Set Architecture Notation 159 Formats 161 Instructions 161 Appendi...

Page 7: ...Big Endian and Little Endian bit reversed format 32 bit general purpose registers cache software support and Fast Simplex Link interfaces Chapter 3 MicroBlaze Signal Interface Description describes t...

Page 8: ...8 www xilinx com MicroBlaze Processor Reference Guide UG081 v14 7 Chapter 1 Introduction Send Feedback...

Page 9: ...mized for implementation in Xilinx Field Programmable Gate Arrays FPGAs Figure 2 1 shows a functional block diagram of the MicroBlaze core Figure 2 1 MicroBlaze Core Block Diagram DXCL_M DXCL_S Data s...

Page 10: ...MicroBlaze Versions v7 30 v8 10 v8 20 v8 30 v8 40 v8 50 Version Status obsolete deprecated deprecated deprecated deprecated preferred Processor pipeline depth 3 5 3 5 3 5 3 5 3 5 3 5 On chip Periphera...

Page 11: ...y Accesses option option option option option option Use Xilinx Cache Link for All D Cache Memory Accesses option option option option option option Use Write back Caching Policy for D Cache option op...

Page 12: ...ion option option option Lockstep support option option option option Configurable use of FPGA primitives option option option option Low latency interrupt mode option option option Swap instructions...

Page 13: ...Endian Byte Significance MSByte LSByte Big Endian Byte Order n n 1 n 2 n 3 Big Endian Byte Reversed Order n 3 n 2 n 1 n Little Endian Byte Address n 3 n 2 n 1 n Little Endian Byte Significance MSByte...

Page 14: ...semantics of each instruction Table 2 5 Instruction Set Nomenclature Symbol Description Ra R0 R31 General Purpose Register source operand a Rb R0 R31 General Purpose Register source operand b Rd R0 R...

Page 15: ...data type All arithmetic operations are performed on signed word operands unless otherwise specified unsigned Operation performed on unsigned integer data type float Operation performed on floating po...

Page 16: ...b 00000000000 Rd Ra Rb MULH Rd Ra Rb 010000 Rd Ra Rb 00000000001 Rd Ra Rb 32 signed MULHU Rd Ra Rb 010000 Rd Ra Rb 00000000011 Rd Ra Rb 32 unsigned MULHSU Rd Ra Rb 010000 Rd Ra Rb 00000000010 Rd Ra si...

Page 17: ...01000100000 Rd 1 if Rb Ra float1 else Rd 0 FCMP LE Rd Ra Rb 010110 Rd Ra Rb 01000110000 Rd 1 if Rb Ra float1 else Rd 0 FCMP GT Rd Ra Rb 010110 Rd Ra Rb 01001000000 Rd 1 if Rb Ra float1 else Rd 0 FCMP...

Page 18: ...se Rd 0 SRA Rd Ra 100100 Rd Ra 0000000000000001 Rd s Ra 1 C Ra 31 SRC Rd Ra 100100 Rd Ra 0000000000100001 Rd C Ra 1 C Ra 31 SRL Rd Ra 100100 Rd Ra 0000000001000001 Rd 0 Ra 1 C Ra 31 SEXT8 Rd Ra 100100...

Page 19: ...x1001 is ZPR SPR 0x1002 is TLBX SPR 0x1003 is TLBLO SPR 0x1004 is TLBHI SPR 0x1005 is TLBSX MFS Rd Sa 100101 Rd 00000 10 Sa Rd SPR Sa where SPR 0x0000 is PC SPR 0x0001 is MSR SPR 0x0003 is EAR SPR 0x0...

Page 20: ...11 10000 Ra Rb 00000000000 PC PC Rb if Ra 0 BNED Ra Rb 100111 10001 Ra Rb 00000000000 PC PC Rb if Ra 0 BLTD Ra Rb 100111 10010 Ra Rb 00000000000 PC PC Rb if Ra 0 BLED Ra Rb 100111 10011 Ra Rb 00000000...

Page 21: ...Imm 101111 00101 Ra Imm PC PC s Imm if Ra 0 BEQID Ra Imm 101111 10000 Ra Imm PC PC s Imm if Ra 0 BNEID Ra Imm 101111 10001 Ra Imm PC PC s Imm if Ra 0 BLTID Ra Imm 101111 10010 Ra Imm PC PC s Imm if R...

Page 22: ...tore is successful the sequence of instructions from the semaphore load to the semaphore store appear to be executed atomically no other device modified the semaphore location between SB Rd Ra Rb SBR...

Page 23: ...the processor A conditional sequence begins with an LWX instruction It can be followed by memory accesses and or computations on the loaded value The sequence ends with an SWX instruction In most case...

Page 24: ...fer if write back cache and victim buffers are used Software must ensure that the modified instructions have been written to memory before being fetched by the processor The annotated code below shows...

Page 25: ...software conventions on general purpose register usage 0 31 R0 R31 Figure 2 2 R0 R31 Table 2 7 General Purpose Registers R0 R31 Bits Name Description Reset Value 0 31 R0 Always has a value of zero An...

Page 26: ...can be written using either an MTS instruction or the dedicated MSRSET and MSRCLR instructions When writing to the MSR using MSRSET or MSRCLR the Carry bit takes effect immediately and the remaining...

Page 27: ...Virtual Access protection enabled with C_USE_MMU 2 Protection Only available when configured with an MMU if C_USE_MMU 1 and C_AREA_OPTIMIZED 0 Read Write 0 19 UMS User Mode Save Only available when co...

Page 28: ...se hardware divider C_USE_DIV 1 Read Write 0 26 ICE Instruction Cache Enable 0 Instruction Cache disabled 1 Instruction Cache enabled Only available if configured to use instruction cache C_USE_ICACHE...

Page 29: ...ction Storage Exception Data TLB Miss Exception Instruction TLB Miss Exception cannot be disabled and are not affected by this bit 2 This bit is only used for integer divide by zero or divide overflow...

Page 30: ...s accessed An instruction storage exception that specifies the virtual effective address read A data TLB miss exception that specifies the virtual effective address accessed An instruction TLB miss ex...

Page 31: ...on Reset Value 0 18 Reserved 19 DS Delay Slot Exception 0 not caused by delay slot instruction 1 caused by delay slot instruction Read only 0 20 26 ESS Exception Specific Status For details refer to T...

Page 32: ...tion 20 26 Reserved 0 Instruction bus error 20 ECC Exception caused by ILMB correctable or uncorrectable error 0 21 26 Reserved 0 Data bus error 20 ECC Exception caused by DLMB correctable or uncorrec...

Page 33: ...n the BTR is specified by setting Sa 0x000B The BTR register is illustrated in Figure 2 7 and Table 2 13 provides bit descriptions and reset values Instruction storage 20 DIZ Instruction storage Zone...

Page 34: ...a Register stores data read on a stream link FSL or AXI that caused a stream exception The contents of this register is undefined for all other exceptions When read with the MFS instruction the EDR is...

Page 35: ...High Register SHR The Stack High Register stores the stack high limit use to detect stack underflow When the address of a load or store instruction using the stack pointer register R1 as rA is greater...

Page 36: ...a 0x1000 The register is accessible according to the memory management special registers parameter C_MMU_TLB_ACCESS PID is also used when accessing a TLB entry When writing Translation Look Aside Buff...

Page 37: ...rs parameter C_MMU_TLB_ACCESS Figure 2 13 illustrates the ZPR register and Table 2 19 provides bit descriptions and reset values 0 2 4 6 8 10 12 14 16 18 20 22 24 26 28 30 ZP0 ZP1 ZP2 ZP3 ZP4 ZP5 ZP6...

Page 38: ...te The UTLB is not reset by the external reset inputs Reset MB_Reset and Debug_Rst Figure 2 14 illustrates the TLBLO register and Table 2 20 provides bit descriptions and reset values 0 22 23 24 28 29...

Page 39: ...the parameter C_DCACHE_USE_WRITEBACK is set to 1 this bit controls caching policy A write through policy is selected when set to 1 and a write back policy is selected otherwise This bit is fixed to 1...

Page 40: ...TLBHI and MSR UM is not set the value in the TID field is stored in PID The UTLB is reset on bit stream download reset value is 0x00000000 for all TLBHI entries Note The UTLB is not reset by the exter...

Page 41: ...an or as a little endian page otherwise The E bit only affects data read or data write accesses Instruction accesses are not affected The E bit is only implemented when the parameter C_USE_REORDER_INS...

Page 42: ...e 2 16 TLBX Table 2 22 Translation Look Aside Buffer Index Register TLBX Bits Name Description Reset Value 0 MISS TLB Miss This bit is cleared to 0 when the TLBSX register is written with a virtual ad...

Page 43: ...and Table 2 23 provides bit descriptions and reset values 0 22 31 VPN Reserved Figure 2 17 TLBSX Table 2 23 Translation Look Aside Buffer Index Search Register TLBSX Bits Name Description Reset Value...

Page 44: ...MUL Use hardware multiplier C_USE_HW_MUL 0 None 4 FPU Use FPU C_USE_FPU 0 None 5 EXC Use any type of exceptions Based on C_ _EXCEPTION Also set if C_USE_MMU 0 None 6 ICU Use instruction cache C_USE_IC...

Page 45: ...e C_I_PLB 8 INTERCON Use PLB interconnect C_INTERCONNECT 1 PLBv46 9 STREAM Use AXI4 Stream interconnect C_STREAM_INTERCONNECT 1 AXI4 Stream 10 ACE Use ACE interconnect C_INTERCONNECT 3 ACE 11 AXI4DP D...

Page 46: ...any illegal opcode C_ILL_OPCODE_EXCEPTION 28 AXIIEXC Generate exception for M_AXI_I error C_M_AXI_I_BUS_EXCEPTION 29 AXIDEXC Generate exception for M_AXI_D error C_M_AXI_D_BUS_EXCEPTION 30 DIVEXC Gen...

Page 47: ...struction cache is used for all memory accesses within the cacheable range C_ICACHE_ALWAYS_USED 17 Reserved 0 18 ICI Instruction cache XCL protocol C_ICACHE_INTERFACE 19 21 ICV Instruction cache victi...

Page 48: ...idth C_DCACHE_DATA_WIDTH 0 26 AXI4DC Data Cache AXI interface uses AXI4 protocol with support for exclusive access C_M_AXI_DC_EXCLUSIVE_ACCESS 27 31 Reserved 0 Table 2 30 Processor Version Register 6...

Page 49: ...e Grade Virtex 6 Q Virtex 7 Defence Grade Virtex 7 Q Kintex 7 Defence Grade Kintex 7 Q Artix 7 Automotive Artix 7 Defence Grade Artix 7 Q Zynq 7000 Automotive Zynq 7000 Defence Grade Zynq 7000 Q 8 31...

Page 50: ...laze Processor Reference Guide UG081 v14 7 Chapter 2 MicroBlaze Architecture Table 2 36 Processor Version Register 12 PVR12 Bits Name Description Value 0 31 VECTORS Location of MicroBlaze vectors C_BA...

Page 51: ...buffer should be emptied before executing the modified instructions to ensure that it does not contain the old unmodified instructions The recommended way to do this is using an MBAR instruction alth...

Page 52: ...en simply changed to the saved target address in case the branch should be taken Unconditional branches and return instructions are always taken whereas conditional branches use branch prediction to a...

Page 53: ...cesses to I O and memory it uses memory mapped I O The processor has up to three interfaces for memory accesses Local Memory Bus LMB Advanced eXtensible Interface AXI4 or Processor Local Bus PLB Advan...

Page 54: ...user mode and virtual mode status is saved in the MSR UMS and VMS bits Application user mode programs transfer control to system service routines privileged mode programs using the BRALID or BRKI inst...

Page 55: ...memory management unit MMU available when C_USE_MMU is set to 3 Virtual and C_AREA_OPTIMIZED is set to 0 The MMU controls effective address to physical address mapping and supports memory protection...

Page 56: ...2 37 System software maintains a page translation table that contains entries used to translate each virtual page into a physical page The page size defined by a page translation entry determines the...

Page 57: ...page size selection enables system software to more efficiently use memory by reducing fragmentation unused memory For example a large data structure can be allocated to a 16 MB page and a small I O...

Page 58: ...ins data page translation entries and is fully associative The page translation entries stored in the DTLB represent the most recently accessed data page translations from the UTLB The DTLB is used to...

Page 59: ...icy for the data cache write back or write through whether a page is cacheable and how bytes are ordered endianness Table 2 37 shows the relationship between the TLB entry SIZE field and the translate...

Page 60: ...to load the TLB with multiple entries that match an EA EPN and PID combination However this is considered a programming error and results in undefined behavior When a hit occurs the MMU reads the RPN...

Page 61: ...B entry specifies a zone field that prevents access to the page ZPR Zn 00 This applies to load and store instructions The TLB entry specifies a read only page TLBLO WR 0 that is not otherwise overridd...

Page 62: ...led MSR VM 1 an instruction TLB miss exception occurs if a valid matching TLB entry was not found in the TLB shadow and UTLB Any instruction fetch can cause an instruction TLB miss exception Access Pr...

Page 63: ...tain any number of pages specifying any combination of page sizes There is no requirement for a zone to contain adjacent pages The zone protection register ZPR is a 32 bit register used to specify the...

Page 64: ...Instead system software can use the TLB miss exceptions and the data storage exception to collect this information As the information is collected it can be stored in a data structure associated with...

Page 65: ...ith future releases of EDK support software All of these events will clear the reservation bit used together with the LWX and SWX instructions to implement mutual exclusion such as semaphores and spin...

Page 66: ...manner For the MMU exceptions Data Storage Exception Instruction Storage Exception Data TLB Miss Exception Instruction TLB Miss Exception the register R17 is loaded with the appropriate program count...

Page 67: ..._USE_CE_EXCEPTION is set to 1 and a correctable error occurs in the LMB memory as indicated by the ICE signal The CacheLink IXCL interfaces cannot cause instruction bus exceptions Illegal Opcode Excep...

Page 68: ...operand or by illegal infinite or zero operand combinations Privileged Instruction Exception The Privileged Instruction exception is caused by an attempt to execute a privileged instruction in User Mo...

Page 69: ..._NM_BRK input ports On a break the instruction in the execution stage completes while the instruction in the decode stage is replaced by a branch to the break vector address C_BASE_VECTORS 0x18 The br...

Page 70: ...uction in the decode stage at the time of the interrupt is automatically loaded into general purpose register R14 In addition the processor also disables future interrupts by clearing the IE bit in th...

Page 71: ...t Service Routine ISR from the time an interrupt occurs depends on the configuration of the processor and the latency of the memory controller storing the interrupt vectors If MicroBlaze is configured...

Page 72: ...le segment size must be 2N where N is a positive integer The range specified by C_ICACHE_BASEADDR and C_ICACHE_HIGHADDR must comprise a complete power of two range such that range 2N and the N least s...

Page 73: ...in a tag or instruction Block RAM The instruction cache always issues burst accesses for the CacheLink interface whereas it only issues burst accesses for the AXI4 interface when 32 bit data width is...

Page 74: ...sing the hardware debug logic of MicroBlaze WIC Instruction The optional WIC instruction C_ALLOW_ICACHE_WR 1 is used to invalidate cache lines in the instruction cache from an application For a detail...

Page 75: ...of cacheable memory When selecting cache sizes below 2 kB distributed RAM is used to implement the Tag RAM and Data RAM except that block RAM is always used for the Data RAM when C_AREA_OPTIMIZED is...

Page 76: ...ith the write through protocol a store to an address within the cacheable range generates an equivalent byte halfword or word write over the data AXI4 interface or the data CacheLink to external memor...

Page 77: ...nsure that all the prior writes within the cacheable range have been completed in external memory before reading back over M_AXI_DP or PLB This can be done by writing to a semaphore immediately before...

Page 78: ...n The optional WDC instruction C_ALLOW_DCACHE_WR 1 is used to invalidate or flush cache lines in the data cache from an application For a detailed description please refer to Chapter 5 MicroBlaze Inst...

Page 79: ...SR This method is commonly referred to as Flush to Zero FTZ An operation on a quiet NaN returns the fixed NaN 0xFFC00000 rather than one of the NaN operands Overflow as a result of a floating point op...

Page 80: ...perations addition fadd subtraction fsub multiplication fmul division fdiv square root fsqrt available if C_USE_FPU 2 EXTENDED Comparison The FPU implements the following floating point comparisons co...

Page 81: ...one operation can be ongoing at any time C Language Programming To gain maximum benefit from the FPU without low level assembly language programming it is important to consider how the C compiler wil...

Page 82: ...ot functions sqrt result in inefficient emulation routines being used instead of FPU instructions include math h float x 1 0F x sqrt x uses double precision Here the math h header is included to avoid...

Page 83: ...pposite direction Both instructions come in 4 flavors blocking data non blocking data blocking control and non blocking control For a detailed description of the get and put instructions please refer...

Page 84: ...which can only be read Support for multiple processors Whenever Microblaze is halted the MB_Halted output signal is set to 1 for example after a breakpoint or watchpoint is hit after a stop XMD comma...

Page 85: ...eaving the LMB BRAM unprotected by disabling C_ECC in the configuration dialogs of all connected LMB BRAM Interface Controllers In this case the internal MicroBlaze block RAM protection is still enabl...

Page 86: ...s used When a parity error is detected during an address translation a TLB miss exception occurs forcing software to reload the entry When a new TLB entry is written using the TLBHI and TLBLO register...

Page 87: ...st The Timer Counter instance void MicroBlazeScrubHandler void CallBackRef u8 TmrCtrNumber Perform other timer interrupt processing here microblaze_scrub int main void int Status Initialize the timer...

Page 88: ...n it would expire once only XTmrCtr_SetOptions TimerCounterInst TIMER_CNTR_0 XTC_INT_MODE_OPTION XTC_AUTO_RELOAD_OPTION Set a reset value for the timer counter such that it will expire earlier than le...

Page 89: ...First Failing Address Register in each of the LMB BRAM Interface Controllers To be able to generate an interrupt C_ECC_STATUS_REGISTERS must be set to 1 in the connected LMB BRAM Interface Controller...

Page 90: ...ch the address for the access into the Correctable Error First Failing Address Register and set the CE_STATUS bit in the ECC Status Register An interrupt will be generated triggering MicroBlaze to rea...

Page 91: ...rk Use Cases Two common use cases are described here In addition lockstep operation provides the basis for implementing triple modular redundancy on MicroBlaze core level Tamper Protection This applic...

Page 92: ...ster MicroBlaze core drive the peripherals in the system The slave MicroBlaze core only has inputs connected all outputs are left open The system contains the basic building block for designing a comp...

Page 93: ...ection Application BRAM Controller BRAM Controller ILMB DLMB BRAM MicroBlaze Debug Module MicroBlaze Slave Debug C_LOCKSTEP_SLAVE 1 MicroBlaze Master Debug C_LOCKSTEP_SLAVE 0 Error Reset Comparator Lo...

Page 94: ...94 www xilinx com MicroBlaze Processor Reference Guide UG081 v14 7 Chapter 2 MicroBlaze Architecture Send Feedback...

Page 95: ...eLink interface is intended for use with specialized external memory controllers MicroBlaze also supports up to 16 Fast Simplex Link FSL or AXI4 Stream interface ports each with one master and one sla...

Page 96: ...ave interfaces DRFSL0 15 FSL slave direct connection interfaces DXCL Data side Xilinx CacheLink interface FSL master slave pair M_AXI_DC Data side cache AXI4 interface M_ACE_DC Data side cache ACE int...

Page 97: ...r Write data M_AXI_DP_WSTRB M_AXI_DP O Master Write strobes M_AXI_DP_WLAST M_AXI_DP O Master Write last M_AXI_DP_WVALID M_AXI_DP O Master Write valid M_AXI_DP_WREADY M_AXI_DP I Slave Write ready M_AXI...

Page 98: ...M_AXI_IP_AWQOS M_AXI_IP O Master Quality of Service M_AXI_IP_AWVALID M_AXI_IP O Master Write address valid M_AXI_IP_AWREADY M_AXI_IP I Slave Write address ready M_AXI_IP_WDATA M_AXI_IP O Master Write...

Page 99: ...O Master Burst type M_AXI_DC_AWLOCK M_AXI_DC O Master Lock type M_AXI_DC_AWCACHE M_AXI_DC O Master Cache type M_AXI_DC_AWPROT M_AXI_DC O Master Protection type M_AXI_DC_AWQOS M_AXI_DC O Master Quality...

Page 100: ..._DC_ARVALID M_AXI_DC O Master Read address valid M_AXI_DC_ARREADY M_AXI_DC I Slave Read address ready M_AXI_DC_ARUSER M_AXI_DC O Master Read address user signals M_AXI_DC_ARDOMAIN M_ACE_DC O Master Re...

Page 101: ...HE M_AXI_IC O Master Cache type M_AXI_IC_AWPROT M_AXI_IC O Master Protection type M_AXI_IC_AWQOS M_AXI_IC O Master Quality of Service M_AXI_IC_AWVALID M_AXI_IC O Master Write address valid M_AXI_IC_AW...

Page 102: ...dy M_AXI_IC_ARUSER M_AXI_IC O Master Read address user signals M_AXI_IC_ARDOMAIN M_ACE_IC O Master Read address domain M_AXI_IC_ARSNOOP M_ACE_IC O Master Read address snoop M_AXI_IC_ARBAR M_ACE_IC O M...

Page 103: ...DPLB O Data Interface PLB bus request priority DPLB_M_rdBurst DPLB O Data Interface PLB burst read transfer indicator DPLB_M_request DPLB O Data Interface PLB bus request DPLB_M_RNW DPLB O Data Inter...

Page 104: ...byte enables IPLB_M_busLock IPLB O Instruction Interface PLB bus lock IPLB_M_lockErr IPLB O Instruction Interface PLB lock error indicator IPLB_M_MSize IPLB O Instruction Interface PLB master data bus...

Page 105: ...B_MSSize IPLB I Instruction Interface PLB slave data bus size IPLB_MTimeout IPLB I Instruction Interface PLB bus timeout Data_Addr 0 31 DLMB O Data interface LMB address bus Byte_Enable 0 3 DLMB O Dat...

Page 106: ...s write data Sn_AXIS_TVALID S0_AXIS S15_AXIS I Slave interface input AXI4 channels write valid Sn_AXIS_TREADY S0_AXIS S15_AXIS O Slave interface output AXI4 channels write ready FSL0_M FSL15_M MFSL or...

Page 107: ...I Wake MicroBlaze from sleep mode when either or both bits are set to 1 Ignored if MicroBlaze is not in sleep mode Dbg_Wakeup Core O Debug request that external logic should wake MicroBlaze from slee...

Page 108: ...ache is enabled C_INTERCONNECT_M_AXI_IC_READ_ISSUING is set to 8 since it must be a power of two How memory locations are accessed depend on the parameter C_ICACHE_ALWAYS_USED If the parameter is 1 th...

Page 109: ..._DC_DATA_WIDTH 32 Default single word accesses and burst accesses with C_DCACHE_LINE_LEN word busts used Write bursts are only used when C_DCACHE_USE_WRITEBACK is set to 1 128 Used when C_DCACHE_DATA_...

Page 110: ...ority 8 1000 M_AXI_IC C_M_AXI_IC_ARCACHE Memory Type Write back Read and Write allocate 1111 M_ACE_IC C_M_AXI_IC_ARCACHE Memory Type normal access Write back Read and Write allocate 1111 Memory Type D...

Page 111: ...MSR Read Operation A read from the stream interface is performed by MicroBlaze using one of the get or getd instructions A read operations transfers the contents of an input AXI4 interface to a gener...

Page 112: ...puts from the core and indicate which byte lanes of the data bus contain valid data Byte_Enable 0 3 is valid only when AS is high In multicycle accesses accesses requiring more than one clock cycle to...

Page 113: ...next clock cycle then Read_Strobe remains high Write_Strobe The write strobe is an output from the core and indicates that a write transfer is in progress This signal goes high in the first clock cyc...

Page 114: ...ta word in local memory has been corrected before writing the new data UE The UE signal is an input to the core and indicates that the current transfer had an uncorrectable error It is valid on the ri...

Page 115: ...s Figure 3 3 LMB Generic Write Operation N Wait States Clk Addr Byte_Enable Data_Write AS Read_Strobe Write_Strobe Data_Read Ready Wait CE UE A0 BE0 D0 Don t Care Figure 3 4 LMB Generic Read Operation...

Page 116: ...eric Read Operation N Wait States Clk Addr Byte_Enable Data_Write AS Read_Strobe Write_Strobe Data_Read Ready Wait CE UE A0 D0 Don t Care Figure 3 6 LMB Back to Back Write Operation Clk Addr Byte_Enab...

Page 117: ...7 LMB Back to Back Read Operation Figure 3 8 Back to Back Mixed Write Read Operation 0 Wait States Clk Addr Byte_Enable Data_Write AS Read_Strobe Write_Strobe Data_Read Ready Wait CE UE A0 Don t Care...

Page 118: ...pter 3 MicroBlaze Signal Interface Description Figure 3 9 Back to Back Mixed Write Read Operation N Wait States Clk Addr Byte_Enable Data_Write AS Read_Strobe Write_Strobe Data_Read Ready Wait CE UE A...

Page 119: ...Data steering for read cycles are shown in Table 3 6 and Table 3 7 and data steering for write cycles are shown in Table 3 8 and Table 3 9 Table 3 6 Big Endian Read Data Steering Load to Register rD A...

Page 120: ...te Data Steering Store from Register rD Address 30 31 Byte_Enable 0 3 Transfer Size Write Data Bus Bytes Byte0 Byte1 Byte2 Byte3 11 0001 byte rD 24 31 10 0010 byte rD 24 31 01 0100 byte rD 24 31 00 10...

Page 121: ...al Name Description VHDL Type Direction FSLn_M_Clk Clock std_logic input FSLn_M_Write Write enable signal indicating that data is being written to the output FSL std_logic output FSLn_M_Data Data valu...

Page 122: ...h prefix n the transfer is completed in one or two clock cycles irrespective of whether or not the FSL was empty In the case the FSL was empty the transfer of data does not take place and the carry bi...

Page 123: ..._ALWAYS_USED for the data cache If the parameter is 1 the cached memory range is always accessed via the CacheLink If the parameter is 0 the cached memory range is accessed over PLB whenever the cache...

Page 124: ...gic output ICACHE_FSL_OUT_Full FSL access buffer for I side read accesses is full std_logic input DCACHE_FSL_IN_Clk Clock output to D side return read data FSL std_logic output DCACHE_FSL_IN_Read Read...

Page 125: ...EDK IP Documentation The CacheLink solution uses one incoming slave and one outgoing master FSL per cache controller The outgoing FSL is used to send access requests while the incoming FSL is used fo...

Page 126: ...ts goes high to indicate that data is available Note There must be at least one clock cycle before ICACHE_FSL_IN_Exists goes high that is at least one wait state must be used With the IXCL protocol cr...

Page 127: ...30 31 of the address are used to encode burst access 0b10 burst To separate a burst access from a single byte write the control bit for the first data word in step 4 is low for a burst access DCACHE_...

Page 128: ...put Lockstep_Out Output with all comparison signals from both master and slaves std_logic output Table 3 14 MicroBlaze Lockstep Comparison Signals Signal Name Bus Index Range VHDL Type MB_Halted 0 std...

Page 129: ...DPLB_M_TAttribute 444 to 459 std_logic_vector DPLB_M_type 460 to 462 std_logic_vector DPLB_M_wrDBus1 463 to 590 std_logic_vector ICACHE_FSL_IN_Clk 591 std_logic ICACHE_FSL_IN_Read 592 std_logic ICACHE...

Page 130: ...IP_ARPROT 814 to 816 std_logic_vector M_AXI_IP_ARQOS 817 to 820 std_logic_vector M_AXI_IP_ARVALID 821 std_logic M_AXI_IP_RREADY 822 std_logic M_AXI_DP_AWID 823 std_logic M_AXI_DP_AWADDR 824 to 855 std...

Page 131: ...EADY 1608 n 35 std_logic M_AXI_IC_AWID 2133 std_logic M_AXI_IC_AWADDR 2134 to 2165 std_logic_vector M_AXI_IC_AWLEN 2166 to 2173 std_logic_vector M_AXI_IC_AWSIZE 2174 to 2176 std_logic_vector M_AXI_IC_...

Page 132: ...2 2858 std_logic M_AXI_IC_ACREADY2 2859 std_logic M_AXI_IC_CRVALID2 2860 std_logic M_AXI_IC_CRRESP2 2861 to 2865 std_logic_vector M_AXI_IC_CDVALID2 2866 std_logic M_AXI_IC_CDLAST2 2867 std_logic M_AXI...

Page 133: ...d_logic_vector M_AXI_DC_ARSNOOP2 3586 to 3589 std_logic_vector M_AXI_DC_ARBAR2 3590 to 3591 std_logic_vector M_AXI_DC_RREADY 3592 std_logic M_AXI_DC_RACK2 3593 std_logic M_AXI_DC_ACREADY2 3594 std_log...

Page 134: ...3810 std_logic Trace_DCache_Read 3811 std_logic Trace_ICache_Req 3812 std_logic Trace_ICache_Hit 3813 std_logic Trace_ICache_Rdy 3814 std_logic Trace_OF_PipeRun 3815 std_logic Trace_EX_PipeRun 3816 st...

Page 135: ...All unused Trace exception types are reserved Table 3 15 MicroBlaze Debug Signals Signal Name Description VHDL Type Direction Dbg_Clk JTAG clock from MDM std_logic input Dbg_TDI JTAG TDI from MDM std...

Page 136: ...n D Cache range std_logic output Trace_DCache_Hit Data memory address is present in D Cache std_logic output Trace_DCache_Rdy Data memory address is within D Cache range and the access is completed st...

Page 137: ...01 Unaligned exception 00010 Illegal Opcode exception 00011 Instruction Bus exception 00100 Data Bus exception 00101 Divide exception 00110 FPU exception 00111 Privileged instruction exception1 01010...

Page 138: ...lly backward compatibility Note Shaded rows indicate that the parameter has a fixed value and cannot be modified Table 3 18 MPD Parameters Parameter Name Feature Description Allowable Values Default V...

Page 139: ...0xa0 0x00 std_logic_vector C_INSTANCE Instance Name Any instance name micro blaze yes string C_D_PLB Data side PLB interface 0 1 0 yes integer C_D_AXI Data side AXI interface 0 1 0 yes integer C_D_LM...

Page 140: ...ger C_IPLB_BUS_EXCEPTION Enable exception handling for IPLB bus error 0 1 0 integer C_DPLB_BUS_EXCEPTION Enable exception handling for DPLB bus error 0 1 0 integer C_M_AXI_I_BUS_EXCEPTION Enable excep...

Page 141: ...integer C_EDGE_IS_POSITIVE Negative Positive Edge Interrupt 0 1 1 yes integer C_FSL_LINKS2 Number of stream interfaces FSL or AXI 0 16 0 yes integer C_FSL_DATA_SIZE FSL data bus size 32 32 NA integer...

Page 142: ...struction cache data width 0 32 bits 1 Full cache line 2 512 bits 0 1 2 0 integer C_ADDR_TAG_BITS Instruction cache address tags 0 25 17 yes integer C_CACHE_BYTE_SIZE Instruction cache size 64 128 256...

Page 143: ...he victims 0 2 4 8 0 integer C_DCACHE_DATA_WIDTH Data cache data width 0 32 bits 1 Full cache line 2 512 bits 0 1 2 0 integer C_DCACHE_ADDR_TAG Data cache address tags 0 25 17 yes integer C_DCACHE_BYT...

Page 144: ...size 1 2 4 8 4 integer C_MMU_ITLB_SIZE5 Instruction shadow Translation Look Aside Buffer size 1 2 4 8 2 integer C_MMU_TLB_ACCESS5 Access to memory management special registers 0 Minimal 1 Read 2 Writ...

Page 145: ...h 32 32 integer C_M_AXI_DP_ SUPPORTS_THREADS Data side AXI uses threads 0 0 integer C_M_AXI_DP_SUPPORTS_READ Data side AXI support for read accesses 1 1 integer C_M_AXI_DP_SUPPORTS_WRITE Data side AXI...

Page 146: ...support 0 0 integer C_M_AXI_IP_PROTOCOL Instruction side AXI protocol AXI4LITE AXI4 LITE string C_INTERCONNECT_ M_AXI_IP_READ_ISSUING Instruction side AXI read accesses issued 1 1 integer C_M_AXI_DC_...

Page 147: ...che AXI read accesses issued 1 2 2 integer C_INTERCONNECT_ M_AXI_DC_WRITE_ISSUING Data cache AXI write accesses issued 1 2 4 8 16 32 32 integer C_M_AXI_IC_ THREAD_ID_WIDTH Instruction cache AXI ID wid...

Page 148: ...elect AXI4 Stream interconnect 0 1 0 integer C_Mn_AXIS_PROTOCOL AXI4 Stream protocol GENERIC GENERIC string C_Sn_AXIS_PROTOCOL AXI4 Stream protocol GENERIC GENERIC string C_Mn_AXIS_DATA_WIDTH AXI4 Str...

Page 149: ...x7 artix7 artix7l qartix7 qartix7l Kintex kintex7 kintex7l qkintex7 qkintex7l Spartan aspartan3 aspartan3a aspartan3adsp aspartan3e aspartan6 qspartan6 qspartan6l spartan3 spartan3a spartan3adsp spart...

Page 150: ...150 www xilinx com MicroBlaze Processor Reference Guide UG081 v14 7 Chapter 3 MicroBlaze Signal Interface Description Send Feedback...

Page 151: ...tible with the compiler generated code Interrupt and Exception handling is also explained briefly Data Types The data types used by MicroBlaze assembly programs are shown in Table 4 1 Data types such...

Page 152: ...r Service ID with attribute svc_table_handler R19 Non volatile SW Must be saved across function calls Callee save R20 Dedicated or Non volatile SW Reserved for storing a pointer to the Global Offset T...

Page 153: ...ng the values in the small data read write section Register R1 stores the value of the stack pointer and is updated on entry and exit from functions Register R18 is used as a temporary register for as...

Page 154: ...he stack is maintained are shown in Figure 4 1 High Address Function Parameters for called sub routine Arg n Arg1 Optional Maximum number of arguments required for any called procedure from the curren...

Page 155: ...ed for the small data areas The small data area is accessed using the read write small data area anchor R13 and a 16 bit offset Allocating small variables to this area reduces the requirement of addin...

Page 156: ...n_handler 0x10 imm high bits of address interrupt handler 0x14 bri _interrupt_handler 0x20 imm high bits of address HW exception handler 0x24 bri _hw_exception_handler With low latency interrupt mode...

Page 157: ...andler ID The first attribute ensures that the compiler will emit an indirect call to the handler with a brki rD 0x8 instruction and emit an rtbd instruction to return from the handler This means that...

Page 158: ...158 www xilinx com MicroBlaze Processor Reference Guide UG081 v14 7 Chapter 4 MicroBlaze Application Binary Interface Send Feedback...

Page 159: ...ined in Table 5 1 Table 5 1 Symbol Notation Symbol Meaning Add Subtract Multiply Divide Bitwise logical AND Bitwise logical OR Bitwise logical XOR x Bitwise logical complement of x Assignment Right sh...

Page 160: ...loating point true if x is or isPosInfinite x Floating point true if x is isNegInfinite x Floating point true if x isNaN x Floating point true if x is a quiet or signalling NaN isZero x Floating point...

Page 161: ...ontains the opcode one destination and one source registers and a source 16 bit immediate value Instructions This section provides descriptions of MicroBlaze instructions Instructions are listed in al...

Page 162: ...the instruction is set to one addc addkc the content of the carry flag MSR C affects the execution of the instruction When bit 4 is cleared add addk the content of the carry flag does not affect the...

Page 163: ...one addic addikc the content of the carry flag MSR C affects the execution of the instruction When bit 4 is cleared addi addik the content of the carry flag does not affect the execution of the instr...

Page 164: ...Set Architecture and Logical AND Description The contents of register rA are ANDed with the contents of register rB the result is placed into register rD Pseudocode rD rA rB Registers Altered rD Laten...

Page 165: ...egister rD Pseudocode rD rA sext IMM Registers Altered rD Latency 1 cycle Note By default Type B Instructions will take the 16 bit IMM field value and sign extend it to 32 bits to use as the immediate...

Page 166: ...andn Logical AND NOT Description The contents of register rA are ANDed with the logical complement of the contents of register rB the result is placed into register rD Pseudocode rD rA rB Registers A...

Page 167: ...esult is placed into register rD Pseudocode rD rA sext IMM Registers Altered rD Latency 1 cycle Note By default Type B Instructions will take the 16 bit IMM field value and sign extend it to 32 bits t...

Page 168: ...ing the target instruction If the D bit is not set it means that there is no delay slot so the instruction to be executed after the branch is the target instruction Pseudocode If rA 0 then PC PC rB el...

Page 169: ...else PC PC 4 if D 1 then allow following instruction to complete execution Registers Altered PC Latency 1 cycle if branch is not taken or successful branch prediction occurs 2 cycles if branch is take...

Page 170: ...ing the target instruction If the D bit is not set it means that there is no delay slot so the instruction to be executed after the branch is the target instruction Pseudocode If rA 0 then PC PC rB el...

Page 171: ...else PC PC 4 if D 1 then allow following instruction to complete execution Registers Altered PC Latency 1 cycle if branch is not taken or successful branch prediction occurs 2 cycles if branch is take...

Page 172: ...ng the target instruction If the D bit is not set it means that there is no delay slot so the instruction to be executed after the branch is the target instruction Pseudocode If rA 0 then PC PC rB els...

Page 173: ...lse PC PC 4 if D 1 then allow following instruction to complete execution Registers Altered PC Latency 1 cycle if branch is not taken or successful branch prediction occurs 2 cycles if branch is taken...

Page 174: ...ing the target instruction If the D bit is not set it means that there is no delay slot so the instruction to be executed after the branch is the target instruction Pseudocode If rA 0 then PC PC rB el...

Page 175: ...else PC PC 4 if D 1 then allow following instruction to complete execution Registers Altered PC Latency 1 cycle if branch is not taken or successful branch prediction occurs 2 cycles if branch is take...

Page 176: ...ng the target instruction If the D bit is not set it means that there is no delay slot so the instruction to be executed after the branch is the target instruction Pseudocode If rA 0 then PC PC rB els...

Page 177: ...lse PC PC 4 if D 1 then allow following instruction to complete execution Registers Altered PC Latency 1 cycle if branch is not taken or successful branch prediction occurs 2 cycles if branch is taken...

Page 178: ...ng the target instruction If the D bit is not set it means that there is no delay slot so the instruction to be executed after the branch is the target instruction Pseudocode If rA 0 then PC PC rB els...

Page 179: ...lse PC PC 4 if D 1 then allow following instruction to complete execution Registers Altered PC Latency 1 cycle if branch is not taken or successful branch prediction occurs 2 cycles if branch is taken...

Page 180: ...there is a branch delay slot or not If the D bit is set it means that there is a delay slot and the instruction following the branch that is in the branch delay slot is allowed to complete execution b...

Page 181: ...Instructions Note The instructions brl and bral are not available A delay slot must not be used by the following imm branch or break instructions Interrupts and external hardware breaks are deferred...

Page 182: ...the branch that is in the branch delay slot is allowed to complete execution before executing the target instruction If the D bit is not set it means that there is no delay slot so the instruction to...

Page 183: ...re not available By default Type B Instructions will take the 16 bit IMM field value and sign extend it to 32 bits to use as the immediate operand This behavior can be overridden by preceding the Type...

Page 184: ...n bit will be cleared When MicroBlaze is configured to use an MMU C_USE_MMU 1 this instruction is privileged This means that if the instruction is attempted in User Mode MSR UM 1 a Privileged Instruct...

Page 185: ...ister bits User Mode and Virtual Mode are cleared Pseudocode if MSR UM and IMM C_BASE_VECTORS 0x8 and IMM C_BASE_VECTORS 0x18 then ESR EC 00111 else rD PC PC sext IMM MSR BIP 1 Reservation 0 if IMM C_...

Page 186: ...he barrel shift performed is Arithmetical The mnemonics bsrl and bsll clear the T bit and the shift performed is Logical Pseudocode if S 1 then rD rA rB 27 31 else if T 1 then if rB 27 31 0 then rD 0...

Page 187: ...sll clear the T bit and the shift performed is Logical Pseudocode if S 1 then rD rA IMM else if T 1 then if IMM 0 then rD 0 IMM 1 rA 0 rD IMM 31 rA IMM else rD rA else rD rA IMM Registers Altered rD L...

Page 188: ...e most significant bit The result is a number between 0 and 32 stored in register rD The result in rD is 32 when rA is 0 and it is 0 if rA is 0xFFFFFFFF Pseudocode n 0 while rA n 0 n n 1 rD n Register...

Page 189: ...r rD The MSB bit of rD is adjusted to shown true relation between rA and rB If the U bit is set rA and rB is considered unsigned values If the U bit is clear rA and rB is considered signed values Pseu...

Page 190: ...000 FSR IO 1 ESR EC 00110 else if isQuietNaN rA or isQuietNaN rB then rD 0xFFC00000 else if isDnz rA rB then rD signZero rA rB FSR UF 1 ESR EC 00110 else if isNaN rA rB then rD signInfinite rA rB FSR...

Page 191: ...0xFFC00000 FSR IO 1 ESR EC 00110 else if isQuietNaN rA or isQuietNaN rB then rD 0xFFC00000 else if isDnz rB rA then rD signZero rB rA FSR UF 1 ESR EC 00110 else if isNaN rB rA then rD signInfinite rB...

Page 192: ...rA then rD 0xFFC00000 FSR IO 1 ESR EC 00110 else if isQuietNaN rA or isQuietNaN rB then rD 0xFFC00000 else if isDnz rB rA then rD signZero rA rB FSR UF 1 ESR EC 00110 else if isNaN rB rA then rD signI...

Page 193: ...sQuietNaN rB then rD 0xFFC00000 else if isZero rA and not isInfinite rB then rD signInfinite rB rA FSR DZ 1 ESR EC 00110 else if isDnz rB rA then rD signZero rB rA FSR UF 1 ESR EC 00110 else if isNaN...

Page 194: ...ister is unchanged ESR EC if an FP exception is generated FSR IO DO Latency 1 cycle with C_AREA_OPTIMIZED 0 3 cycles with C_AREA_OPTIMIZED 1 Note These instructions are only available when the MicroBl...

Page 195: ...1 ESR EC 00110 rD 1 Less than 001 rD 0 rD 1 rD 0 rD 0 FSR IO 1 ESR EC 00110 rD 0 FSR IO 1 ESR EC 00110 Equal 010 rD 0 rD 0 rD 1 rD 0 FSR IO 1 ESR EC 00110 rD 0 Less or equal 011 rD 0 rD 1 rD 1 rD 0 F...

Page 196: ...nt and puts the result in register rD This is a 32 bit rounding signed conversion that will produce a 32 bit floating point result Pseudocode rD float rA Registers Altered rD Latency 4 cycles with C_A...

Page 197: ...ESR EC 00110 else if isNaN rA then rD 0xFFC00000 FSR IO 1 ESR EC 00110 else if isInf rA or rA 231 or rA 231 1 then rD 0xFFC00000 FSR IO 1 ESR EC 00110 else rD int rA Registers Altered rD unless an FP...

Page 198: ...IO 1 ESR EC 00110 else if isQuietNaN rA then rD 0xFFC00000 else if rA 0 then rD 0xFFC00000 FSR IO 1 ESR EC 00110 else if rA 0 then rD 0 else rD sqrt rA Registers Altered rD unless an FP exception is...

Page 199: ...n e bit is 1 will generate an exception if there is a control bit mismatch In this case ESR is updated with EC set to the exception cause and ESS set to the link index The target register rD is not up...

Page 200: ...all the pipeline of MicroBlaze until the instruction can be completed Interrupts are served when the parameter C_USE_EXTENDED_FSL_INSTR is set to 1 and the instruction is not atomic Note To refer to a...

Page 201: ...SR FSL to 1 The exception versions when e bit is 1 will generate an exception if there is a control bit mismatch In this case ESR is updated with EC set to the exception cause and ESS set to the link...

Page 202: ...with C_AREA_OPTIMIZED 0 2 cycles with C_AREA_OPTIMIZED 1 The blocking versions of this instruction will stall the pipeline of MicroBlaze until the instruction can be completed Interrupts are served un...

Page 203: ...alue in rD will be 2147483648 unless an exception is generated Pseudocode if rA 0 then rD 0 MSR DZO 1 ESR EC 00101 ESR DEC 0 else if U 0 and rA 1 and rB 2147483648 then rD 2147483648 MSR DZO 1 ESR EC...

Page 204: ...tion with an imm instruction The imm instruction locks the 16 bit IMM value temporarily for the next instruction A Type B instruction that immediately follows the imm instruction will then form a 32 b...

Page 205: ...allowed zone protection This only applies to accesses with user mode and virtual protected mode enabled Pseudocode Addr rA rB if TLB_Miss Addr and MSR VM 1 then ESR EC 10010 ESR S 0 MSR UMS MSR UM MS...

Page 206: ...IMM if TLB_Miss Addr and MSR VM 1 then ESR EC 10010 ESR S 0 MSR UMS MSR UM MSR VMS MSR VM MSR UM 0 MSR VM 0 else if Access_Protected Addr and MSR UM 1 and MSR VM 1 then ESR EC 10000 ESR S 0 ESR DIZ 1...

Page 207: ...and virtual protected mode enabled An unaligned data access exception occurs if the least significant bit in the address is not zero Pseudocode Addr rA rB if TLB_Miss Addr and MSR VM 1 then ESR EC 100...

Page 208: ...ss Addr and MSR VM 1 then ESR EC 10010 ESR S 0 MSR UMS MSR UM MSR VMS MSR VM MSR UM 0 MSR VM 0 else if Access_Protected Addr and MSR UM 1 and MSR VM 1 then ESR EC 10000 ESR S 0 ESR DIZ 1 MSR UMS MSR U...

Page 209: ...ast significant bits in the address are not zero Pseudocode Addr rA rB if TLB_Miss Addr and MSR VM 1 then ESR EC 10010 ESR S 0 MSR UMS MSR UM MSR VMS MSR VM MSR UM 0 MSR VM 0 else if Access_Protected...

Page 210: ...0 MSR UMS MSR UM MSR VMS MSR VM MSR UM 0 MSR VM 0 else if Access_Protected Addr and MSR UM 1 and MSR VM 1 then ESR EC 10000 ESR S 0 ESR DIZ 1 MSR UMS MSR UM MSR VMS MSR VM MSR UM 0 MSR VM 0 else if Ad...

Page 211: ...n AXI4 interconnect with exclusive access enabled is used and the interconnect response is not EXOKAY which means that an exclusive access cannot be handled Enabling AXI exclusive access ensures that...

Page 212: ...S if an exception is generated ESR DIZ if a data storage exception is generated Latency 1 cycle with C_AREA_OPTIMIZED 0 2 cycles with C_AREA_OPTIMIZED 1 Note This instruction is used together with SW...

Page 213: ...ode MSR UM 1 a Privileged Instruction exception occurs When the most significant bit in IMM is set to 1 and no exception occurs MicroBlaze enters sleep mode after all outstanding accesses have been co...

Page 214: ...case 0x1001 rD ZPR case 0x1002 rD TLBX case 0x1003 rD TLBLO case 0x1004 rD TLBHI case 0x200x rD PVR x where x 0 to 12 default rD Undefined Registers Altered rD Latency 1 cycle Notes To refer to specia...

Page 215: ...arameter C_FSL_EXCEPTION is set to 1 and the parameter C_FSL_LINKS is greater than 0 FSR is only valid as an operand when the C_USE_FPU parameter is greater than 0 SLR and SHR are only valid as an ope...

Page 216: ...e Carry bit immediately while the remaining bits will take effect one cycle after the instruction has been executed When clearing the IE bit it is guaranteed that the processor will not react to any i...

Page 217: ...MSR ESR EC in case a privileged instruction exception is generated Latency 1 cycle Notes MSRSET will affect the Carry bit immediately while the remaining bits will take effect one cycle after the ins...

Page 218: ...Blaze Processor Reference Guide UG081 v14 7 Chapter 5 MicroBlaze Instruction Set Architecture When setting MSR VM the instruction must always be followed by a synchronizing branch instruction for exam...

Page 219: ...case 0x0001 MSR rA case 0x0007 FSR rA case 0x0800 SLR rA case 0x0802 SHR rA case 0x1000 PID rA case 0x1001 ZPR rA case 0x1002 TLBX rA case 0x1003 TLBLO rA case 0x1004 TLBHI rA case 0x1005 TLBSX rA if...

Page 220: ..._FPU is greater than 0 The SLR and SHR are only valid as a destination if the MicroBlaze parameter C_USE_STACK_PROTECTION is set to 1 PID ZPR and TLBSX are only valid as destinations when the paramete...

Page 221: ...The least significant word of this value is placed in rD The most significant word is discarded Pseudocode rD LSW rA rB Registers Altered rD Latency 1 cycle with C_AREA_OPTIMIZED 0 3 cycles with C_ARE...

Page 222: ...scarded Pseudocode rD MSW rA rB signed Registers Altered rD Latency 1 cycle with C_AREA_OPTIMIZED 0 3 cycles with C_AREA_OPTIMIZED 1 Note This instruction is only valid if the target architecture has...

Page 223: ...eudocode rD MSW rA rB unsigned Registers Altered rD Latency 1 cycle with C_AREA_OPTIMIZED 0 3 cycles with C_AREA_OPTIMIZED 1 Note This instruction is only valid if the target architecture has multipli...

Page 224: ...d is discarded Pseudocode rD MSW rA signed rB unsigned signed Registers Altered rD Latency 1 cycle with C_AREA_OPTIMIZED 0 3 cycles with C_AREA_OPTIMIZED 1 Note This instruction is only valid if the t...

Page 225: ...ext IMM Registers Altered rD Latency 1 cycle with C_AREA_OPTIMIZED 0 3 cycles with C_AREA_OPTIMIZED 1 Notes By default Type B Instructions will take the 16 bit IMM field value and sign extend it to 32...

Page 226: ...cription The contents of register rA are ORed with the contents of register rB the result is placed into register rD Pseudocode rD rA rB Registers Altered rD Latency 1 cycle Note The assembler pseudo...

Page 227: ...ister rD Pseudocode rD rA sext IMM Registers Altered rD Latency 1 cycle Note By default Type B Instructions will take the 16 bit IMM field value and sign extend it to 32 bits to use as the immediate o...

Page 228: ...as position 1 and comparing until LSB as position 4 If none of the byte pairs match rD is set to 0 Pseudocode if rB 0 7 rA 0 7 then rD 1 else if rB 8 15 rA 8 15 then rD 2 else if rB 16 23 rA 16 23 th...

Page 229: ...ents in register rB rD is loaded with 1 if they match and 0 if not Pseudocode if rB rA then rD 1 else rD 0 Registers Altered rD Latency 1 cycle Note This instruction is only available when the paramet...

Page 230: ...mpared with the contents in register rB rD is loaded with 0 if they match and 1 if not Pseudocode if rB rA then rD 0 else rD 1 Registers Altered rD Latency 1 cycle Note This instruction is only availa...

Page 231: ...1 will be handled as the normal case except that the write signal to the link is not asserted thus no source register is required Atomic versions when a bit is 1 are not interruptible This means that...

Page 232: ...upts are served when the parameter C_USE_EXTENDED_FSL_INSTR is set to 1 and the instruction is not atomic Note To refer to an FSLx interface in assembly language use rfsl0 rfsl1 rfsl15 The blocking ve...

Page 233: ...o 1 The test versions when t bit is 1 will be handled as the normal case except that the write signal to the link is not asserted thus no source register is required Atomic versions when a bit is 1 ar...

Page 234: ...ions of this instruction will stall the pipeline of MicroBlaze until the instruction can be completed Interrupts are served unless the instruction is atomic which ensures that the instruction cannot b...

Page 235: ...the carry flag will be affected by the execution of the instruction When bit 4 of the instruction is set to one rsubc rsubkc the content of the carry flag MSR C affects the execution of the instructi...

Page 236: ...tent of the carry flag MSR C affects the execution of the instruction When bit 4 is cleared rsubi rsubik the content of the carry flag does not affect the execution of the instruction providing a norm...

Page 237: ...U C_USE_MMU 1 this instruction is privileged This means that if the instruction is attempted in User Mode MSR UM 1 a Privileged Instruction exception occurs Pseudocode if MSR UM 1 then ESR EC 00111 el...

Page 238: ...User Mode MSR UM 1 a Privileged Instruction exception occurs With low latency interrupt mode C_USE_INTERRUPT 2 the Interrupt_Ack output port is set to 10 when this instruction is executed and subseque...

Page 239: ...struction to complete execution MSR EE 1 MSR EIP 0 MSR UM MSR UMS MSR VM MSR VMS ESR 0 Registers Altered PC MSR EE MSR EIP MSR UM MSR VM ESR Latency 2 cycles Note Convention is to use general purpose...

Page 240: ...ore the branch target Pseudocode PC rA sext IMM allow following instruction to complete execution Registers Altered PC Latency 1 cycle if successful branch prediction occurs 2 cycles with Branch Targe...

Page 241: ...nd access is prevented by no access allowed or read only zone protection No access allowed can only occur in user mode Pseudocode Addr rA rB if TLB_Miss Addr and MSR VM 1 then ESR EC 10010 ESR S 1 MSR...

Page 242: ...ddr rA sext IMM if TLB_Miss Addr and MSR VM 1 then ESR EC 10010 ESR S 1 MSR UMS MSR UM MSR VMS MSR VM MSR UM 0 MSR VM 0 else if Access_Protected Addr and MSR VM 1 then ESR EC 10000 ESR S 1 ESR DIZ No...

Page 243: ...tion sign extends a halfword 16 bits into a word 32 bits Bit 16 in rA will be copied into bits 0 15 of rD Bits 16 31 in rA will be copied into bits 16 31 of rD Pseudocode rD 0 15 rA 16 rD 16 31 rA 16...

Page 244: ...iption This instruction sign extends a byte 8 bits into a word 32 bits Bit 24 in rA will be copied into bits 0 23 of rD Bits 24 31 in rA will be copied into bits 24 31 of rD Pseudocode rD 0 23 rA 24 r...

Page 245: ...only occur in user mode An unaligned data access exception occurs if the least significant bit in the address is not zero Pseudocode Addr rA rB if TLB_Miss Addr and MSR VM 1 then ESR EC 10010 ESR S 1...

Page 246: ...TLB_Miss Addr and MSR VM 1 then ESR EC 10010 ESR S 1 MSR UMS MSR UM MSR VMS MSR VM MSR UM 0 MSR VM 0 else if Access_Protected Addr and MSR VM 1 then ESR EC 10000 ESR S 1 ESR DIZ No access allowed MSR...

Page 247: ...t and places the result in rD The most significant bit of rA that is the sign bit placed in the most significant bit of rD The least significant bit coming out of the shift chain is placed in the Carr...

Page 248: ...to the right and places the result in rD The Carry flag is shifted in the shift chain and placed in the most significant bit of rD The least significant bit coming out of the shift chain is placed in...

Page 249: ...ight and places the result in rD A zero is shifted in the shift chain and placed in the most significant bit of rD The least significant bit coming out of the shift chain is placed in the Carry flag P...

Page 250: ...naligned data access exception occurs if the two least significant bits in the address are not zero Pseudocode Addr rA rB if TLB_Miss Addr and MSR VM 1 then ESR EC 10010 ESR S 1 MSR UMS MSR UM MSR VMS...

Page 251: ...e sequence in the register between endianness formats either from little endian to big endian or vice versa Pseudocode rD 24 31 rA 0 7 rD 16 23 rA 8 15 rD 8 15 rA 16 23 rD 0 7 rA 24 31 Registers Alter...

Page 252: ...n rD This effectively converts the two halfwords in the register between endianness formats either from little endian to big endian or vice versa Pseudocode rD 0 15 rA 16 31 rD 16 31 rA 0 15 Registers...

Page 253: ...C 10010 ESR S 1 MSR UMS MSR UM MSR VMS MSR VM MSR UM 0 MSR VM 0 else if Access_Protected Addr and MSR VM 1 then ESR EC 10000 ESR S 1 ESR DIZ No access allowed MSR UMS MSR UM MSR VMS MSR VM MSR UM 0 MS...

Page 254: ...read only zone protection No access allowed can only occur in user mode An unaligned data access exception will not occur even if the two least significant bits in the address are not zero Enabling A...

Page 255: ...Z if a data storage exception is generated Latency 1 cycle with C_AREA_OPTIMIZED 0 2 cycles with C_AREA_OPTIMIZED 1 Note This instruction is used together with LWX to implement exclusive access such a...

Page 256: ...contains the address of the affected cache line and the register rB value is not used If the E bit is set to 1 MicroBlaze will request that the matching address in an external cache should be invalida...

Page 257: ...wdc clear instruction is intended to invalidate a specific area in memory for example a buffer to be written by a Direct Memory Access device Using this instruction ensures that other cache lines are...

Page 258: ...en ESR EC 00111 else if C_ICACHE_LINE_LEN 4 then cacheline_mask 1 log2 C_CACHE_BYTE_SIZE 4 1 ICache Line Ra 4 cacheline_mask Tag 0 if C_ICACHE_LINE_LEN 8 then cacheline_mask 1 log2 C_CACHE_BYTE_SIZE 5...

Page 259: ...gical Exclusive OR Description The contents of register rA are XORed with the contents of register rB the result is placed into register rD Pseudocode rD rA rB Registers Altered rD Latency 1 cycle xor...

Page 260: ...e extended IMM field the result is placed into register rD Pseudocode rD rA sext IMM Registers Altered rD Latency 1 cycle Note By default Type B Instructions will take the 16 bit IMM field value and s...

Page 261: ...XPS Help SDK Help PowerPC 405 Processor Reference Guide UG011 Additional Resources The following lists some of the resources you can access directly using the provided URLs The entire set of GNU manu...

Page 262: ...262 www xilinx com MicroBlaze Processor Reference Guide UG081 v14 7 Send Feedback...

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