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MicroBlaze Processor Reference Guide
UG081 (v14.7)
Chapter 2:
MicroBlaze Architecture
Equivalent Pseudocode
PC
←
C_BASE_V 0x00000000
MSR
←
C_RESET_MSR (see
“MicroBlaze Core Configurability” in Chapter 3
EAR
←
0; ESR
←
0; FSR
←
0
PID
←
0; ZPR
←
0; TLBX
←
0
Reservation
←
0
Hardware Exceptions
MicroBlaze can be configured to trap the following internal error conditions: illegal instruction,
instruction and data bus error, and unaligned access. The divide exception can only be enabled if the
processor is configured with a hardware divider (
C_USE_DIV=1
). When configured with a
hardware floating point unit (
C_USE_FPU>0
), it can also trap the following floating point specific
exceptions: underflow, overflow, float division-by-zero, invalid operation, and denormalized
operand error.
When configured with a hardware Memory Management Unit, it can also trap the following
memory management specific exceptions: Illegal Instruction Exception, Data Storage Exception,
Instruction Storage Exception, Data TLB Miss Exception, and Instruction TLB Miss Exception.
A hardware exception causes MicroBlaze to flush the pipeline and branch to the hardware exception
vector (address
C_BASE_VECTORS
+ 0x20). The execution stage instruction in the exception cycle
is not executed.
The exception also updates the general purpose register R17 in the following manner:
•
For the MMU exceptions (Data Storage Exception, Instruction Storage Exception, Data TLB
Miss Exception, Instruction TLB Miss Exception) the register R17 is loaded with the
appropriate program counter value to re-execute the instruction causing the exception upon
return. The value is adjusted to return to a preceding
IMM
instruction, if any. If the exception is
caused by an instruction in a branch delay slot, the value is adjusted to return to the branch
instruction, including adjustment for a preceding
IMM
instruction, if any.
•
For all other exceptions the register R17 is loaded with the program counter value of the
subsequent instruction, unless the exception is caused by an instruction in a branch delay slot.
If the exception is caused by an instruction in a branch delay slot, the ESR[DS] bit is set. In
this case the exception handler should resume execution from the branch target address stored
in BTR.
The EE and EIP bits in MSR are automatically reverted when executing the
RTED
instruction.
The VM and UM bits in MSR are automatically reverted from VMS and UMS when executing the
RTED
,
RTBD
, and
RTID
instructions.
Exception Priority
When two or more exceptions occur simultaneously, they are handled in the following order, from
the highest priority to the lowest:
•
Instruction Bus Exception
•
Instruction TLB Miss Exception
•
Instruction Storage Exception
•
Illegal Opcode Exception
•
Privileged Instruction Exception or Stack Protection Violation Exception
•
Data TLB Miss Exception
•
Data Storage Exception
